From e4500c653057759e219418a104c2f2224480e0de Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 1 Jun 2023 21:42:12 +0200 Subject: [PATCH] soc/amd/common/acpi/pci_root: introduce ROOT_BRIDGE macro When instantiated in the DSDT, this macro will expand to the static part of the PCIe root bridge device. This macro allows both to deduplicate parts of the DSDT code as well as adding more than one PCIe root bridge device in the DSDT. Signed-off-by: Felix Held Signed-off-by: Arthur Heymans Change-Id: I6f20d694bc86da3c3c9c00fb10eecdaed1f666a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75568 Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/soc/amd/common/acpi/pci_root.asl | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 src/soc/amd/common/acpi/pci_root.asl diff --git a/src/soc/amd/common/acpi/pci_root.asl b/src/soc/amd/common/acpi/pci_root.asl new file mode 100644 index 0000000000..46d15b7b8d --- /dev/null +++ b/src/soc/amd/common/acpi/pci_root.asl @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define ROOT_BRIDGE(acpi_name) \ + Device(acpi_name) { \ + Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ \ + Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ \ + Method (_OSC, 4, NotSerialized) { \ + /* Check for proper PCI/PCIe UUID */ \ + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) \ + { \ + /* Let OS control everything */ \ + Return(Arg3) \ + } Else { \ + CreateDWordField(Arg3, 0, CDW1) \ + CDW1 = CDW1 | 4 /* Unrecognized UUID, so set bit 2 to 1 */ \ + Return(Arg3) \ + } \ + } \ + }