incomplete (wrong) support for this chip.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1359 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
parent
688b385aec
commit
e45714874e
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config chip.h
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object superio.o
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#ifndef PNP_INDEX_REG
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#define PNP_INDEX_REG 0x15C
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#endif
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#ifndef PNP_DATA_REG
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#define PNP_DATA_REG 0x15D
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#endif
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#ifndef SIO_COM1
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#define SIO_COM1_BASE 0x3F8
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#endif
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#ifndef SIO_COM2
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#define SIO_COM2_BASE 0x2F8
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#endif
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extern struct chip_control superio_winbond_w83627thf_control;
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struct superio_winbond_w83627thf_config {
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struct com_ports com1, com2;
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struct lpt_ports lpt;
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int port;
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};
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/* Copyright 2000 AG Electronics Ltd. */
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/* This code is distributed without warranty under the GPL v2 (see COPYING) */
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#include <arch/io.h>
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#include <device/device.h>
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#include <device/chip.h>
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#include <console/console.h>
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#include <string.h>
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#include <bitops.h>
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#include "chip.h"
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void pnp_output(char address, char data)
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{
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outb(address, PNP_INDEX_REG);
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outb(data, PNP_DATA_REG);
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}
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static void sio_enable(struct chip *chip, enum chip_pass pass)
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{
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struct superio_NSC_pc87360_config *conf = (struct superio_NSC_pc87360_config *)chip->chip_info;
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switch (pass) {
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case CONF_PASS_PRE_CONSOLE:
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/* Enable Super IO Chip */
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pnp_output(0x07, 6); /* LD 6 = UART1 */
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pnp_output(0x30, 0); /* Dectivate */
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pnp_output(0x60, conf->port >> 8); /* IO Base */
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pnp_output(0x61, conf->port & 0xFF); /* IO Base */
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pnp_output(0x30, 1); /* Activate */
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break;
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default:
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/* nothing yet */
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break;
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}
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}
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static void pnp_write_config(device_t dev, unsigned char value, unsigned char reg)
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{
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outb(reg, dev->path.u.pnp.port);
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outb(value, dev->path.u.pnp.port + 1);
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}
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static unsigned char pnp_read_config(device_t dev, unsigned char reg)
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{
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outb(reg, dev->path.u.pnp.port);
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return inb(dev->path.u.pnp.port + 1);
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}
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static void pnp_set_logical_device(device_t dev)
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{
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pnp_write_config(dev, dev->path.u.pnp.device, 0x07);
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}
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static void pnp_set_enable(device_t dev, int enable)
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{
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pnp_write_config(dev, enable?0x1:0x0, 0x30);
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}
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static int pnp_read_enable(device_t dev)
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{
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return !!pnp_read_config(dev, 0x30);
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}
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#define FLOPPY_DEVICE 0
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#define PARALLEL_DEVICE 1
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#define COM2_DEVICE 2
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#define COM1_DEVICE 3
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#define SWC_DEVICE 4
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#define MOUSE_DEVICE 5
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#define KBC_DEVICE 6
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#define GPIO_DEVICE 7
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#define ACB_DEVICE 8
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#define FSCM_DEVICE 9
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#define WDT_DEVICE 10
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struct io_info {
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unsigned mask, set;
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};
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struct pnp_info {
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unsigned flags;
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#define PNP_IO0 0x01
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#define PNP_IO1 0x02
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#define PNP_IRQ0 0x04
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#define PNP_IRQ1 0x08
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#define PNP_DRQ0 0x10
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#define PNP_DRQ1 0x20
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struct io_info io0, io1;
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};
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static struct pnp_info pnp_dev_info[] = {
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[ 0] = { PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07fa, 0}, },
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[ 1] = { PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x04f8, 0}, },
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[ 2] = { PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, },
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[ 3] = { PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
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[ 4] = { PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, },
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[ 5] = { PNP_IRQ0 },
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[ 6] = { PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, },
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[ 7] = { PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } },
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[ 8] = { PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } },
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[ 9] = { PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } },
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[10] = { PNP_IO0 | PNP_IRQ0, { 0xfffc, 0 } },
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};
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static struct resource *get_resource(device_t dev, unsigned index)
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{
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struct resource *resource;
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int i;
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resource = 0;
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for(i = 0; i < dev->resources; i++) {
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resource = &dev->resource[i];
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if (resource->index == index) {
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break;
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}
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}
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if (!resource || (resource->index != index)) {
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resource = &dev->resource[dev->resources];
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memset(resource, 0, sizeof(*resource));
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dev->resources++;
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}
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/* Initialize the resource values */
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if (!(resource->flags & IORESOURCE_FIXED)) {
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resource->flags = 0;
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resource->base = 0;
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}
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resource->size = 0;
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resource->limit = 0;
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resource->flags = 0;
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resource->index = index;
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resource->align = 0;
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resource->gran = 0;
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return resource;
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}
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static void pnp_read_ioresource(device_t dev, unsigned index, struct io_info *info)
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{
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struct resource *resource;
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uint32_t size;
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resource = get_resource(dev, index);
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/* Initilize the resource */
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resource->limit = 0xffff;
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resource->flags |= IORESOURCE_IO;
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/* Set the resource size and alignment */
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size = (0xffff & info->mask);
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resource->size = (~(size | 0xfffff800) + 1);
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resource->align = log2(resource->size);
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resource->gran = resource->align;
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}
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static void pnp_read_resources(device_t dev)
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{
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struct pnp_info *info;
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struct resource *resource;
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pnp_set_logical_device(dev);
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info = &pnp_dev_info[dev->path.u.pnp.device];
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if (info->flags & PNP_IO0) {
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pnp_read_ioresource(dev, 0x60, &info->io0);
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}
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if (info->flags & PNP_IO1) {
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pnp_read_ioresource(dev, 0x62, &info->io1);
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}
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if (info->flags & PNP_IRQ0) {
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resource = get_resource(dev, 0x70);
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resource->size = 1;
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resource->flags |= IORESOURCE_IRQ;
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}
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if (info->flags & PNP_IRQ1) {
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resource = get_resource(dev, 0x72);
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resource->size = 1;
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resource->flags |= IORESOURCE_IRQ;
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}
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if (info->flags & PNP_DRQ0) {
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resource = get_resource(dev, 0x74);
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resource->size = 1;
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resource->flags |= IORESOURCE_DRQ;
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}
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if (info->flags & PNP_DRQ1) {
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resource = get_resource(dev, 0x75);
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resource->size = 1;
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resource->flags |= IORESOURCE_DRQ;
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}
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}
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static void pnp_set_iobase(device_t dev, unsigned iobase, unsigned index)
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{
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/* Index == 0x60 or 0x62 */
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pnp_write_config(dev, (iobase >> 8) & 0xff, index);
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pnp_write_config(dev, iobase & 0xff, index + 1);
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}
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static void pnp_set_irq(device_t dev, unsigned irq, unsigned index)
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{
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/* Index == 0x70 or 0x72 */
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pnp_write_config(dev, irq, index);
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}
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static void pnp_set_drq(device_t dev, unsigned drq, unsigned index)
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{
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/* Index == 0x74 */
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pnp_write_config(dev, drq & 0xff, index);
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}
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static void pnp_set_resource(device_t dev, struct resource *resource)
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{
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if (!(resource->flags & IORESOURCE_SET)) {
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#if 1
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printk_err("ERROR: %s %02x not allocated\n",
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dev_path(dev), resource->index);
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#endif
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return;
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}
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if (resource->flags & IORESOURCE_IO) {
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pnp_set_iobase(dev, resource->base, resource->index);
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}
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else if (resource->flags & IORESOURCE_DRQ) {
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pnp_set_drq(dev, resource->base, resource->index);
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}
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else if (resource->flags & IORESOURCE_IRQ) {
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pnp_set_irq(dev, resource->base, resource->index);
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}
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else {
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printk_err("ERROR: %s %02x unknown resource type\n",
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dev_path(dev), resource->index);
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return;
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}
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printk_debug(
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"%s %02x <- [0x%08lx - 0x%08lx %s\n",
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dev_path(dev),
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resource->index,
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resource->base, resource->base + resource->size - 1,
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(resource->flags & IORESOURCE_IO)? "io":
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(resource->flags & IORESOURCE_DRQ)? "drq":
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(resource->flags & IORESOURCE_IRQ)? "irq":
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(resource->flags & IORESOURCE_MEM)? "mem":
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"???");
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}
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static void pnp_set_resources(device_t dev)
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{
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int i;
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pnp_set_logical_device(dev);
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for(i = 0; i < dev->resources; i++) {
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pnp_set_resource(dev, &dev->resource[i]);
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}
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}
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static void pnp_enable_resources(device_t dev)
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{
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 1);
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}
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static void pnp_enable(device_t dev)
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{
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pnp_set_logical_device(dev);
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if (!dev->enable) {
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pnp_set_enable(dev, 0);
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}
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}
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static struct device_operations pnp_ops = {
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.read_resources = pnp_read_resources,
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.set_resources = pnp_set_resources,
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.enable_resources = pnp_enable_resources,
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.enable = pnp_enable,
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};
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#define MAX_FUNCTION 10
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static void enumerate(struct chip *chip)
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{
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struct superio_NSC_pc87360_config *conf = (struct superio_NSC_pc87360_config *)chip->chip_info;
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struct resource *resource;
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struct device_path path;
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device_t dev;
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int i;
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chip_enumerate(chip);
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path.type = DEVICE_PATH_PNP;
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path.u.pnp.port = chip->dev->path.u.pnp.port;
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/* Set the ops on the newly allocated devices */
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for(i = 0; i <= WDT_DEVICE; i++) {
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path.u.pnp.device = i;
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dev = alloc_find_dev(chip->bus, &path);
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dev->ops = &pnp_ops;
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}
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/* Processes the hard codes for com1 */
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path.u.pnp.device = COM1_DEVICE;
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dev = alloc_find_dev(chip->bus, &path);
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resource = get_resource(dev, 0x60);
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if (conf->com1.base) {
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resource->base = conf->com1.base;
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resource->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_SET;
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}
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resource = get_resource(dev, 0x70);
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if (conf->com1.irq) {
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resource->base = conf->com1.irq;
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resource->flags = IORESOURCE_IRQ | IORESOURCE_FIXED | IORESOURCE_SET;
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}
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/* Process the hard codes for the keyboard controller */
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path.u.pnp.device = KBC_DEVICE;
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dev = alloc_find_dev(dev, &path);
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resource = get_resource(dev, 0x60);
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resource->base = 0x60;
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resource->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_SET;
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resource = get_resource(dev, 0x62);
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resource->base = 0x64;
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resource->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_SET;
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}
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struct chip_control superio_NSC_pc87360_control = {
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.enable = sio_enable,
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.enumerate = enumerate,
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.name = "winbond w83627thf";
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};
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