GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel: Use simple PCI config access 

Call the simple PCI config accessors directly.

Change-Id: I2c6712d836924b01c33a8435292be1ac2e530472
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Kyösti Mälkki 2019-03-04 07:22:56 +02:00 committed by Nico Huber
parent c8b4d217d0
commit e459a89f0f
3 changed files with 18 additions and 54 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
src/soc/intel/baytrail/iosf.c
View File

@ -13,31 +13,19 @@
* GNU General Public License for more details.
*/
#include <device/mmio.h>
#include <stdint.h>
#include <device/pci_ops.h>
#include <soc/iosf.h>
#if !defined(__PRE_RAM__)
#define IOSF_PCI_BASE (CONFIG_MMCONF_BASE_ADDRESS + (IOSF_PCI_DEV << 12))
static inline void write_iosf_reg(int reg, uint32_t value)
{
pci_s_write_config32(IOSF_PCI_DEV, reg, value);
}
static inline void write_iosf_reg(int reg, uint32_t value)
{
write32((u32 *)(IOSF_PCI_BASE + reg), value);
}
static inline uint32_t read_iosf_reg(int reg)
{
return read32((u32 *)(IOSF_PCI_BASE + reg));
return pci_s_read_config32(IOSF_PCI_DEV, reg);
}
#else
static inline void write_iosf_reg(int reg, uint32_t value)
{
pci_write_config32(IOSF_PCI_DEV, reg, value);
}
static inline uint32_t read_iosf_reg(int reg)
{
return pci_read_config32(IOSF_PCI_DEV, reg);
}
#endif
/* Common sequences for all the port accesses. */
static uint32_t iosf_read_port(uint32_t cr, int reg)

24
src/soc/intel/braswell/iosf.c
View File

@ -14,32 +14,20 @@
* GNU General Public License for more details.
*/
#include <device/mmio.h>
#include <stdint.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <soc/iosf.h>
#if ENV_RAMSTAGE
#define IOSF_PCI_BASE (CONFIG_MMCONF_BASE_ADDRESS + (IOSF_PCI_DEV << 12))
static inline void write_iosf_reg(int reg, uint32_t value)
{
pci_s_write_config32(IOSF_PCI_DEV, reg, value);
}
static inline void write_iosf_reg(int reg, uint32_t value)
{
write32((void *)(IOSF_PCI_BASE + reg), value);
}
static inline uint32_t read_iosf_reg(int reg)
{
return read32((void *)(IOSF_PCI_BASE + reg));
return pci_s_read_config32(IOSF_PCI_DEV, reg);
}
#else
static inline void write_iosf_reg(int reg, uint32_t value)
{
pci_write_config32(IOSF_PCI_DEV, reg, value);
}
static inline uint32_t read_iosf_reg(int reg)
{
return pci_read_config32(IOSF_PCI_DEV, reg);
}
#endif /* ENV_RAMSTAGE */
/* Common sequences for all the port accesses. */
static uint32_t iosf_read_port(uint32_t cr, int reg)

24
src/soc/intel/fsp_baytrail/iosf.c
View File

@ -15,31 +15,19 @@
* GNU General Public License for more details.
*/
#include <device/mmio.h>
#include <stdint.h>
#include <device/pci_ops.h>
#include <soc/iosf.h>
#if !defined(__PRE_RAM__)
#define IOSF_PCI_BASE (CONFIG_MMCONF_BASE_ADDRESS + (IOSF_PCI_DEV << 12))
static inline void write_iosf_reg(int reg, uint32_t value)
{
pci_s_write_config32(IOSF_PCI_DEV, reg, value);
}
static inline void write_iosf_reg(int reg, uint32_t value)
{
write32((u32 *)(IOSF_PCI_BASE + reg), value);
}
static inline uint32_t read_iosf_reg(int reg)
{
return read32((u32 *)(IOSF_PCI_BASE + reg));
return pci_s_read_config32(IOSF_PCI_DEV, reg);
}
#else
static inline void write_iosf_reg(int reg, uint32_t value)
{
pci_write_config32(IOSF_PCI_DEV, reg, value);
}
static inline uint32_t read_iosf_reg(int reg)
{
return pci_read_config32(IOSF_PCI_DEV, reg);
}
#endif
/* Common sequences for all the port accesses. */
static uint32_t iosf_read_port(uint32_t cr, int reg)