soc/intel/cannonlake: Enable IDT and expection handling support for all stages
Change-Id:I4146a040e5e43bed7ccc6cb0a7dc2271f1e7a8ea Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/26661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -26,6 +26,7 @@ config CPU_SPECIFIC_OPTIONS
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select HAVE_INTEL_FIRMWARE
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select HAVE_MONOTONIC_TIMER
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select HAVE_SMI_HANDLER
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select IDT_IN_EVERY_STAGE
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select INTEL_GMA_ACPI
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select INTEL_GMA_ADD_VBT_DATA_FILE if RUN_FSP_GOP
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select IOAPIC
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