soc/apollolake: Allow enable/disable of LPSS S0ix from devicetree

Change-Id: Ib7aa1d1b32adcb541a155b8ba2ee011cb5bcf784
Signed-off-by: Saurabh Satija <saurabh.satija@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/15055
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

src/soc/intel/apollolake/chip.c

@@ -332,6 +332,8 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
 
 	silconfig->IshEnable = cfg->integrated_sensor_hub_enable;
 
+	silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable;
+
 	/* Disable setting of EISS bit in FSP. */
 	silconfig->SpiEiss = 0;
 }

src/soc/intel/apollolake/chip.h

@@ -101,6 +101,9 @@ struct soc_intel_apollolake_config {
 	uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */
 	uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */
 	uint8_t gpe0_dw3; /* GPE0_127_96 STS/EN */
+
+	/* Configure LPSS S0ix Enable */
+	uint8_t lpss_s0ix_enable;
 };
 
 #endif	/* _SOC_APOLLOLAKE_CHIP_H_ */