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soc/intel/skylake: Move acpi_sci_irq() to acpi.c 

Change-Id: I8bc170bd715e13d46fcedc0f796e2a99786791c0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
This commit is contained in:
Angel Pons 2021-04-17 12:49:08 +02:00 committed by Patrick Georgi
parent 0feb949565
commit e4844ce7c9
5 changed files with 31 additions and 31 deletions
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28
src/soc/intel/skylake/acpi.c
View File

@ -475,6 +475,34 @@ unsigned long northbridge_write_acpi_tables(const struct device *const dev,
return current;
}
int acpi_sci_irq(void)
{
int scis = pci_read_config32(PCH_DEV_PMC, ACTL) & SCI_IRQ_SEL;
int sci_irq = 9;
/* Determine how SCI is routed. */
switch (scis) {
case SCIS_IRQ9:
case SCIS_IRQ10:
case SCIS_IRQ11:
sci_irq = scis - SCIS_IRQ9 + 9;
break;
case SCIS_IRQ20:
case SCIS_IRQ21:
case SCIS_IRQ22:
case SCIS_IRQ23:
sci_irq = scis - SCIS_IRQ20 + 20;
break;
default:
printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n");
sci_irq = 9;
break;
}
printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq);
return sci_irq;
}
unsigned long acpi_madt_irq_overrides(unsigned long current)
{
int sci = acpi_sci_irq();

1
src/soc/intel/skylake/fadt.c
View File

@ -2,6 +2,7 @@
#include <acpi/acpi.h>
#include <cpu/x86/smm.h>
#include <soc/acpi.h>
#include <soc/iomap.h>
#include <soc/pm.h>
#include "chip.h"

2
src/soc/intel/skylake/include/soc/acpi.h
View File

@ -11,6 +11,8 @@
#define PSS_LATENCY_TRANSITION 10
#define PSS_LATENCY_BUSMASTER 10
/* Return the selected ACPI SCI IRQ */
int acpi_sci_irq(void);
unsigned long acpi_madt_irq_overrides(unsigned long current);
unsigned long northbridge_write_acpi_tables(const struct device *,
unsigned long current, struct acpi_rsdp *);

3
src/soc/intel/skylake/include/soc/pm.h
View File

@ -155,9 +155,6 @@ struct chipset_power_state {
uint32_t prev_sleep_state;
} __packed;
/* Return the selected ACPI SCI IRQ */
int acpi_sci_irq(void);
/* Get base address PMC memory mapped registers. */
uint8_t *pmc_mmio_regs(void);

28
src/soc/intel/skylake/pmutil.c
View File

@ -113,34 +113,6 @@ const char *const *soc_std_gpe_sts_array(size_t *gpe_arr)
return gpe_sts_bits;
}
int acpi_sci_irq(void)
{
int scis = pci_read_config32(PCH_DEV_PMC, ACTL) & SCI_IRQ_SEL;
int sci_irq = 9;
/* Determine how SCI is routed. */
switch (scis) {
case SCIS_IRQ9:
case SCIS_IRQ10:
case SCIS_IRQ11:
sci_irq = scis - SCIS_IRQ9 + 9;
break;
case SCIS_IRQ20:
case SCIS_IRQ21:
case SCIS_IRQ22:
case SCIS_IRQ23:
sci_irq = scis - SCIS_IRQ20 + 20;
break;
default:
printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n");
sci_irq = 9;
break;
}
printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq);
return sci_irq;
}
uint8_t *pmc_mmio_regs(void)
{
uint32_t reg32;