diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c
index ea10269c0c..13416f7bc2 100644
--- a/src/cpu/amd/model_10xxx/fidvid.c
+++ b/src/cpu/amd/model_10xxx/fidvid.c
@@ -631,7 +631,11 @@ static u32 needs_NB_COF_VID_update(void)
 	nodes = get_nodes();
 	nb_cof_vid_update = 0;
 	for (i = 0; i < nodes; i++) {
-		if (pci_read_config32(NODE_PCI(i, 3), 0x1FC) & 1) {
+                u32 cpuRev = mctGetLogicalCPUID(i) ;
+                u32 nbCofVidUpdateDefined = (cpuRev & (AMD_FAM10_LT_D));
+		if (nbCofVidUpdateDefined 
+                    && (pci_read_config32(NODE_PCI(i, 3), 0x1FC) 
+                        & NB_COF_VID_UPDATE_MASK)) {
 			nb_cof_vid_update = 1;
 			break;
 		}
diff --git a/src/northbridge/amd/amdht/AsPsDefs.h b/src/northbridge/amd/amdht/AsPsDefs.h
index 3907208290..0f6db9fc75 100644
--- a/src/northbridge/amd/amdht/AsPsDefs.h
+++ b/src/northbridge/amd/amdht/AsPsDefs.h
@@ -229,6 +229,8 @@
 /* F3x1F0 Product Information Register */
 #define NB_PSTATE_MASK 0x00070000 /* NbPstate for CPU rev C3 */
 
+/* F3x1FC Product Information Register */
+#define NB_COF_VID_UPDATE_MASK 1 /* for CPU rev <= C */
 
 #define NM_PS_REG 5			/* number of P-state MSR registers */
 
diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h
index 0e7319bb25..92490975ff 100644
--- a/src/northbridge/amd/amdmct/amddefs.h
+++ b/src/northbridge/amd/amdmct/amddefs.h
@@ -63,6 +63,7 @@
 #define	AMD_DR_GT_B0	(AMD_DR_ALL & ~(AMD_DR_B0))
 #define	AMD_DR_ALL	(AMD_DR_Bx)
 #define	AMD_FAM10_ALL	(AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 )
+#define AMD_FAM10_LT_D  (AMD_FAM10_ALL & ~(AMD_HY_D0))
 #define	AMD_FAM10_GT_B0	(AMD_FAM10_ALL & ~(AMD_DR_B0))
 #define	AMD_DA_Cx       (AMD_DA_C2 | AMD_DA_C3)
 #define	AMD_DR_Cx       (AMD_RB_C2 | AMD_RB_C3 | AMD_DA_Cx)