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Cosmetics in ioapic.c (trivial, no functional changes). 

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5952 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann 2010-10-14 23:40:10 +00:00
parent 212d0a2eae
commit e49903650c
1 changed files with 23 additions and 19 deletions
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34
src/arch/i386/lib/ioapic.c
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@ -34,7 +34,6 @@ static void io_apic_write(u32 ioapic_base, u32 reg, u32 value)
write32(ioapic_base + 0x10, value); write32(ioapic_base + 0x10, value);
} }
void clear_ioapic(u32 ioapic_base) void clear_ioapic(u32 ioapic_base)
{ {
u32 low, high; u32 low, high;
@ -42,8 +41,8 @@ void clear_ioapic(u32 ioapic_base)
printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at 0x%08x\n", ioapic_base); printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at 0x%08x\n", ioapic_base);
/* Read the available number of interrupts */ /* Read the available number of interrupts. */
ioapic_interrupts = (io_apic_read(ioapic_base, 1) >> 16) & 0xff; ioapic_interrupts = (io_apic_read(ioapic_base, 0x01) >> 16) & 0xff;
if (!ioapic_interrupts || ioapic_interrupts == 0xff) if (!ioapic_interrupts || ioapic_interrupts == 0xff)
ioapic_interrupts = 24; ioapic_interrupts = 24;
printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts);
@ -55,7 +54,8 @@ void clear_ioapic(u32 ioapic_base)
io_apic_write(ioapic_base, i * 2 + 0x10, low); io_apic_write(ioapic_base, i * 2 + 0x10, low);
io_apic_write(ioapic_base, i * 2 + 0x11, high); io_apic_write(ioapic_base, i * 2 + 0x11, high);
printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", i, high, low); printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n",
i, high, low);
} }
if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) { if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) {
@ -70,25 +70,25 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
u32 low, high; u32 low, high;
u32 i, ioapic_interrupts; u32 i, ioapic_interrupts;
printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n", ioapic_base); printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n",
printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = %02x\n", ioapic_base);
printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n",
bsp_lapicid); bsp_lapicid);
if (ioapic_id) { if (ioapic_id) {
printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id); printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id);
/* Set IOAPIC ID if it has been specified */ /* Set IOAPIC ID if it has been specified. */
io_apic_write(ioapic_base, 0x00, io_apic_write(ioapic_base, 0x00,
(io_apic_read(ioapic_base, 0x00) & 0xfff0ffff) | (io_apic_read(ioapic_base, 0x00) & 0xfff0ffff) |
(ioapic_id << 24)); (ioapic_id << 24));
} }
/* Read the available number of interrupts */ /* Read the available number of interrupts. */
ioapic_interrupts = (io_apic_read(ioapic_base, 1) >> 16) & 0xff; ioapic_interrupts = (io_apic_read(ioapic_base, 0x01) >> 16) & 0xff;
if (!ioapic_interrupts || ioapic_interrupts == 0xff) if (!ioapic_interrupts || ioapic_interrupts == 0xff)
ioapic_interrupts = 24; ioapic_interrupts = 24;
printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts);
// XXX this decision should probably be made elsewhere, and // XXX this decision should probably be made elsewhere, and
// it's the C3, not the EPIA this depends on. // it's the C3, not the EPIA this depends on.
#if defined(CONFIG_EPIA_VT8237R_INIT) && CONFIG_EPIA_VT8237R_INIT #if defined(CONFIG_EPIA_VT8237R_INIT) && CONFIG_EPIA_VT8237R_INIT
@ -98,18 +98,20 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
#endif #endif
#ifdef IOAPIC_INTERRUPTS_ON_FSB #ifdef IOAPIC_INTERRUPTS_ON_FSB
/* For the Pentium 4 and above APICs deliver their interrupts /*
* For the Pentium 4 and above APICs deliver their interrupts
* on the front side bus, enable that. * on the front side bus, enable that.
*/ */
printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n"); printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n");
io_apic_write(ioapic_base, 0x03, io_apic_read(ioapic_base, 0x03) | (1 << 0)); io_apic_write(ioapic_base, 0x03,
io_apic_read(ioapic_base, 0x03) | (1 << 0));
#endif #endif
#ifdef IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS #ifdef IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n"); printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n");
io_apic_write(ioapic_base, 0x03, 0); io_apic_write(ioapic_base, 0x03, 0);
#endif #endif
/* Enable Virtual Wire Mode */ /* Enable Virtual Wire Mode. */
low = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT; low = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT;
high = bsp_lapicid << (56 - 32); high = bsp_lapicid << (56 - 32);
@ -121,7 +123,8 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
return; return;
} }
printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", 0, high, low); printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n",
0, high, low);
low = DISABLED; low = DISABLED;
high = NONE; high = NONE;
@ -130,6 +133,7 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
io_apic_write(ioapic_base, i * 2 + 0x10, low); io_apic_write(ioapic_base, i * 2 + 0x10, low);
io_apic_write(ioapic_base, i * 2 + 0x11, high); io_apic_write(ioapic_base, i * 2 + 0x11, high);
printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", i, high, low); printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n",
i, high, low);
} }
} }