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vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww26 release and adapt soc 

CPX-SP FSP ww26 release added UPDs to allow FSP serial redirection. Also
update memory map HOB definition file accordingly.

The CPX-SP soc code is updated to direct FSP log to SOL.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ifd86fb710a0b2bdc8a43225b50b24f585d320caf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42840
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jonathan Zhang 2020-06-26 14:36:01 -07:00 committed by Philipp Deppenwiese
parent e69b1af925
commit e4aab352ee
3 changed files with 26 additions and 8 deletions
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4
src/mainboard/ocp/deltalake/romstage.c
View File

@ -14,7 +14,9 @@ static void mainboard_config_gpios(FSPM_UPD *mupd)
static void mainboard_config_iio(FSPM_UPD *mupd)
{
/* To be implemented */
/* Send FSP log message to SOL */
mupd->FspmConfig.SerialIoUartDebugEnable = 1;
mupd->FspmConfig.SerialIoUartDebugIoBase = 0x2f8;
}
void mainboard_memory_init_params(FSPM_UPD *mupd)

24
src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h
View File

@ -594,7 +594,7 @@ typedef struct {
**/
UINT8 NtbXlinkCtlOverride;
/** Offset 0x0100 - PchAdrEn
/** Offset 0x0100 - PchSirqMode
Enable or Disable PchSirqMode
**/
UINT8 PchSirqMode;
@ -633,7 +633,23 @@ typedef struct {
**/
UINT8 PchPciePortLinkSpeed[20];
/** Offset 0x0140
/** Offset 0x0140 - SerialIoUartDebugEnable
Enable SerialIo Uart debug library in FSP.
0:Disable, 1:Enable
**/
UINT8 SerialIoUartDebugEnable;
/** Offset 0x0141
**/
UINT8 UnusedUpdSpace3;
/** Offset 0x0142 - ISA Serial Base selection
Select ISA Serial Base address could be initialized by boot loader. Default is 0x3F8
0x3F8, 0x2F8
**/
UINT16 SerialIoUartDebugIoBase;
/** Offset 0x0144
**/
UINT8 ReservedMemoryInitUpd[16];
} FSP_M_CONFIG;
@ -654,9 +670,9 @@ typedef struct {
**/
FSP_M_CONFIG FspmConfig;
/** Offset 0x0150
/** Offset 0x0154
**/
UINT8 UnusedUpdSpace3[6];
UINT8 UnusedUpdSpace4[2];
/** Offset 0x0156
**/

6
src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h
View File

@ -85,7 +85,7 @@ typedef struct SystemMemoryMapElement {
/* NOTE - Reserved sizes need to be calibrated if any of the above #define values change */
typedef struct SystemMemoryMapHob {
UINT8 reserved1[61];
UINT8 reserved1[58];
UINT32 lowMemBase; // Mem base in 64MB units for below 4GB mem.
UINT32 lowMemSize; // Mem size in 64MB units for below 4GB mem.
@ -99,11 +99,11 @@ typedef struct SystemMemoryMapHob {
UINT8 numberEntries; // Number of Memory Map Elements
SYSTEM_MEMORY_MAP_ELEMENT Element[MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES];
UINT8 reserved3[24417];
UINT8 reserved3[24514];
UINT32 MmiohBase; // MMIOH base in 64MB granularity
UINT8 reserved4[10];
UINT8 reserved4[2];
} SYSTEM_MEMORY_MAP_HOB;