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bayhub bh720: Configure VIH tuning via devicetree 

There's no need to repeat the same code on every board.

Change-Id: I2e19decfe8609fa644e609673a56ee5109bafefa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49831
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2021-01-22 15:12:14 +01:00 committed by Patrick Georgi
parent f06d046c10
commit e4abe7fd5a
6 changed files with 18 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
src/drivers/generic/bayhub/bh720.c
View File

@ -44,6 +44,19 @@ static void bh720_init(struct device *dev)
}
board_bh720(dev);
if (config && config->vih_tuning_value) {
/* Tune VIH */
u32 bh720_pcr_data;
pci_write_config32(dev, BH720_PROTECT,
BH720_PROTECT_OFF | BH720_PROTECT_LOCK_OFF);
bh720_pcr_data = pci_read_config32(dev, BH720_PCR_DrvStrength_PLL);
bh720_pcr_data &= 0xFFFFFF00;
bh720_pcr_data |= config->vih_tuning_value;
pci_write_config32(dev, BH720_PCR_DrvStrength_PLL, bh720_pcr_data);
pci_write_config32(dev, BH720_PROTECT,
BH720_PROTECT_ON | BH720_PROTECT_LOCK_ON);
}
}
static struct device_operations bh720_ops = {

3
src/drivers/generic/bayhub/chip.h
View File

@ -8,4 +8,7 @@
struct drivers_generic_bayhub_config {
/* 1 to enable power-saving mode, 0 to disable */
int power_saving;
/* CLK and DAT tuning values */
uint8_t vih_tuning_value;
};

1
src/mainboard/google/kahlee/variants/nuwani/devicetree.cb
View File

@ -62,6 +62,7 @@ chip soc/amd/stoneyridge
device pci 2.4 on
chip drivers/generic/bayhub
register "power_saving" = "1"
register "vih_tuning_value" = "0x35"
device pci 00.0 on end
end
end #

11
src/mainboard/google/kahlee/variants/nuwani/mainboard.c
View File

@ -77,17 +77,6 @@ void board_bh720(struct device *dev)
write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000001);
write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0);
write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x80000000);
/* Tune VIH */
pci_write_config32(dev, BH720_PROTECT,
BH720_PROTECT_OFF | BH720_PROTECT_LOCK_OFF);
bh720_pcr_data = pci_read_config32(dev, BH720_PCR_DrvStrength_PLL);
bh720_pcr_data &= 0xFFFFFF00;
/* CLK = 3 and DAT = 2 */
bh720_pcr_data |= 0x35;
pci_write_config32(dev, BH720_PCR_DrvStrength_PLL, bh720_pcr_data);
pci_write_config32(dev, BH720_PROTECT,
BH720_PROTECT_ON | BH720_PROTECT_LOCK_ON);
}
const char *smbios_mainboard_manufacturer(void)

1
src/mainboard/google/kahlee/variants/treeya/devicetree.cb
View File

@ -62,6 +62,7 @@ chip soc/amd/stoneyridge
device pci 2.4 on
chip drivers/generic/bayhub
register "power_saving" = "1"
register "vih_tuning_value" = "0x35"
device pci 00.0 on end
end
end #

11
src/mainboard/google/kahlee/variants/treeya/mainboard.c
View File

@ -77,17 +77,6 @@ void board_bh720(struct device *dev)
write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000001);
write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0);
write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x80000000);
/* Tune VIH */
pci_write_config32(dev, BH720_PROTECT,
BH720_PROTECT_OFF | BH720_PROTECT_LOCK_OFF);
bh720_pcr_data = pci_read_config32(dev, BH720_PCR_DrvStrength_PLL);
bh720_pcr_data &= 0xFFFFFF00;
/* CLK = 3 and DAT = 2 */
bh720_pcr_data |= 0x35;
pci_write_config32(dev, BH720_PCR_DrvStrength_PLL, bh720_pcr_data);
pci_write_config32(dev, BH720_PROTECT,
BH720_PROTECT_ON | BH720_PROTECT_LOCK_ON);
}
const char *smbios_mainboard_manufacturer(void)