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mb/google/rex/var/screebo: Set Baseline Power Limit 

This patch allows google/rex mainboard to choose between "Performance"
(PL_PERFORMANCE) and "Baseline" (PL_BASELINE) power limits (PLs).

This is important for platform to meet balance between power and
performance.

The OEM design google/screebo selects baseline power limit to maintain
the balance performance in lower power.

BUG=b:307237761
TEST=Able to build and boot google/screebo.

w/o this patch:

screebo4es-rev1 ~ # cbmem -c -1 | grep "CPU PL"
[INFO ]  CPU PL1 = 15 Watts
[INFO ]  CPU PL2 = 57 Watts
[INFO ]  CPU PL4 = 114 Watts

w/ this patch:

screebo4es-rev1 ~ # cbmem -c -1 | grep "CPU PL"
[INFO ]  CPU PL1 = 15 Watts
[INFO ]  CPU PL2 = 40 Watts
[INFO ]  CPU PL4 = 84 Watts

Change-Id: I43debc5442ae9c01851652beba676ffc102ca27d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit is contained in:
Subrata Banik 2023-10-26 19:36:00 +05:30
parent 56178990be
commit e4ac7b16ef
3 changed files with 63 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
src/mainboard/google/rex/Kconfig
View File

@ -238,4 +238,17 @@ config USE_PM_ACPI_TIMER
config HAVE_SLP_S0_GATE
def_bool n
choice
prompt "Choose desired processor power limits (PLs)"
default PL_BASELINE if BOARD_GOOGLE_MODEL_SCREEBO
default PL_PERFORMANCE
config PL_PERFORMANCE
bool "Performance: Maximum PLs for maximum performance"
config PL_BASELINE
bool "Baseline: Baseline PLs for balanced performance at lower power"
endchoice
endif # BOARD_GOOGLE_REX_COMMON

44
src/mainboard/google/rex/variants/baseboard/rex/ramstage.c
View File

@ -10,6 +10,7 @@
* pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts)
* Following values are for performance config as per document #640982
*/
#if CONFIG(PL_PERFORMANCE)
const struct cpu_tdp_power_limits performance_efficient_limits[] = {
{
.mch_id = PCI_DID_INTEL_MTL_P_ID_2,
@ -51,6 +52,49 @@ const struct cpu_tdp_power_limits power_optimized_limits[] = {
.pl4_power = 64000
},
};
#else
const struct cpu_tdp_power_limits performance_efficient_limits[] = {
{
.mch_id = PCI_DID_INTEL_MTL_P_ID_2,
.cpu_tdp = 15,
.pl1_min_power = 10000,
.pl1_max_power = 15000,
.pl2_min_power = 40000,
.pl2_max_power = 40000,
.pl4_power = 84000
},
{
.mch_id = PCI_DID_INTEL_MTL_P_ID_5,
.cpu_tdp = 15,
.pl1_min_power = 10000,
.pl1_max_power = 15000,
.pl2_min_power = 40000,
.pl2_max_power = 40000,
.pl4_power = 84000
},
};
const struct cpu_tdp_power_limits power_optimized_limits[] = {
{
.mch_id = PCI_DID_INTEL_MTL_P_ID_2,
.cpu_tdp = 15,
.pl1_min_power = 10000,
.pl1_max_power = 15000,
.pl2_min_power = 40000,
.pl2_max_power = 40000,
.pl4_power = 47000
},
{
.mch_id = PCI_DID_INTEL_MTL_P_ID_5,
.cpu_tdp = 15,
.pl1_min_power = 10000,
.pl1_max_power = 15000,
.pl2_min_power = 40000,
.pl2_max_power = 40000,
.pl4_power = 47000
},
};
#endif
void variant_devtree_update(void)
{

6
src/mainboard/google/rex/variants/screebo/overridetree.cb
View File

@ -34,6 +34,12 @@ end
chip soc/intel/meteorlake
register "power_limits_config[MTL_P_282_242_CORE]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 40,
.tdp_pl4 = 84,
}"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC1)" # USB2_C1
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0
register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Port A1