From e4ad801495e276c26de7b5881118941f777483ac Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Tue, 21 Mar 2006 03:38:53 +0000 Subject: [PATCH] cpubug is fine. adding vsm support now. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2222 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/cpu/amd/model_gx2/Config.lb | 1 + src/cpu/amd/model_gx2/cpubug.c | 139 +++++++++++++++----------- src/northbridge/amd/gx2/northbridge.c | 15 ++- src/northbridge/amd/gx2/pll_reset.c | 2 + 4 files changed, 94 insertions(+), 63 deletions(-) diff --git a/src/cpu/amd/model_gx2/Config.lb b/src/cpu/amd/model_gx2/Config.lb index 8fe6dda21d..e05141c5d9 100644 --- a/src/cpu/amd/model_gx2/Config.lb +++ b/src/cpu/amd/model_gx2/Config.lb @@ -5,3 +5,4 @@ dir /cpu/x86/lapic dir /cpu/x86/cache driver model_gx2_init.o object cpubug.o +object vsmsetup.o \ No newline at end of file diff --git a/src/cpu/amd/model_gx2/cpubug.c b/src/cpu/amd/model_gx2/cpubug.c index 02fce1a0b6..34ebdc9285 100644 --- a/src/cpu/amd/model_gx2/cpubug.c +++ b/src/cpu/amd/model_gx2/cpubug.c @@ -1,42 +1,16 @@ -#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include -void -cpubug(void){ - msr_t msr; - int rev; - - msr = rdmsr(GLCP_CHIP_REVID); - - rev = msr.lo & 0xff; - if (rev < 0x20) { - printk_error("%s: rev < 0x20! bailing!\n"); - return; - } - - switch(rev) - { - case 0x20: - pcideadlock(); - eng1398(); - bug752(); - break; - case 0x22: - pcideadlock(); - eng1398(); - eng2900(); - bug 118339(); - break; - case 0x22: - case 0x30: - break; - default: - printk_error("unknown rev %x, bailing\n", rev); - return; - } - bug784(); - bug118253(); - disablememoryreadorder(); -} #if 0 void @@ -55,6 +29,7 @@ bug573(void){ msr.eax &= 0xfff3; wrmsr(MC_GLD_MSR_PM); } +#endif static void pcideadlock(void){ @@ -77,28 +52,29 @@ pcideadlock(void){ /* write serialize memory hole to PCI. Need to to unWS when something is shadowed regardless of cachablility.*/ msr.lo = 0x021212121; - msr.hi = 0x021212121 + msr.hi = 0x021212121; wrmsr( CPU_RCONF_A0_BF, msr); wrmsr( CPU_RCONF_C0_DF, msr); wrmsr( CPU_RCONF_E0_FF, msr); } -;************************************************************************** -;* -;* CPUbug784 -;* -;* Bugtool #784 + #792 -;* -;* Fix CPUID instructions for < 3.0 CPUs -;* -;* Entry: -;* Exit: -;* Modified: -;* -;************************************************************************** +/****************************************************************************/ +/***/ +/** CPUbug784*/ +/***/ +/** Bugtool #784 + #792*/ +/***/ +/** Fix CPUID instructions for < 3.0 CPUs*/ +/***/ +/** Entry:*/ +/** Exit:*/ +/** Modified:*/ +/***/ +/****************************************************************************/ -void cpubug784(void){ - static char *name = "Geode by NSC"; +void bug784(void){ + msr_t msr; +// static char *name = "Geode by NSC"; /* we'll do this the stupid way, for now, but that's the string they want. NO ONE KNOWS why you * would do this -- the OS can figure this type of stuff out! @@ -113,9 +89,9 @@ void cpubug784(void){ wrmsr(0x3007, msr); msr = rdmsr(0x3002); - wrmsr(*0x3008, msr); + wrmsr(0x3008, msr); -; More CPUID to match AMD better. #792 +/* More CPUID to match AMD better. #792*/ msr = rdmsr(0x3009); msr.hi = 0x0C0C0A13D; msr.lo = 0x00000000; @@ -130,7 +106,7 @@ eng1398(void){ msr = rdmsr(MSR_GLCP+0x17); if ((msr.lo & 0xff) < CPU_REV_2_0) { msr = rdmsr(GLCP_SYS_RSTPLL); - i if (msr.lo & (1<> 32); printk_debug("msr will be set to %x:%x\n", msr.hi, msr.lo); - wrmsr(0x1808, msr); + wrmsr(CPU_RCONF_DEFAULT, msr); enable_cache(); wbinvd(); @@ -164,6 +164,7 @@ setup_gx2(void) membytes = sizem * 1048576; + /* we need to set 0x10000029 and 0x40000029 */ msr.hi = 0x20000000 | membytes >>20; msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20); @@ -174,7 +175,13 @@ setup_gx2(void) msr = rdmsr(0x40000029); printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi,msr.lo); - printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi,msr.lo); + /* need to write 10000028 for vsm */ + /* it is a P2D_R, but the two we just wrote have same offset; use same value */ + wrmsr(0x10000028, msr); + msr = rdmsr(0x10000028); + printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi,msr.lo); + + /* now do the default MSR values */ for(i = 0; msr_defaults[i].msr_no; i++) { msr_t msr; @@ -371,12 +378,16 @@ static void enable_dev(struct device *dev) printk_debug("gx2 north: enable_dev\n"); /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { + extern void cpubug(void); printk_debug("DEVICE_PATH_PCI_DOMAIN\n"); + /* cpubug MUST be called before setup_gx2(), so we force the issue here */ + cpubug(); setup_gx2(); dev->ops = &pci_domain_ops; pci_set_method(dev); } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { + printk_debug("DEVICE_PATH_APIC_CLUSTER\n"); dev->ops = &cpu_bus_ops; } diff --git a/src/northbridge/amd/gx2/pll_reset.c b/src/northbridge/amd/gx2/pll_reset.c index a32f678176..e1696fd703 100644 --- a/src/northbridge/amd/gx2/pll_reset.c +++ b/src/northbridge/amd/gx2/pll_reset.c @@ -108,6 +108,7 @@ static const unsigned char pci33_ddr_crt [] = { 26, 2, 3 // 433/289 }; +#if 0 static unsigned int get_memory_speed(void) { unsigned char val, hi, lo; @@ -118,6 +119,7 @@ static unsigned int get_memory_speed(void) return 20000/(hi*10 + lo); } +#endif static void pll_reset(void) {