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mainboard/google/snappy: Override USB2 phy setting 

Fine tune USB2, need to override the following registers.

port#1:
  PERPORTPETXISET=7
  PERPORTTXISET=0

BUG=b:35858164
BRANCH=reef
TEST=built, measured eye diagram on snappy, and reviewed by intel

Change-Id: I461cf8f032b4e70abc9707e6cd3603a62cee448f
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/18590
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Wisley Chen 2017-03-06 07:00:57 -05:00 committed by Martin Roth
parent 8c247a2a79
commit e4c85c128a
1 changed files with 6 additions and 0 deletions
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6
src/mainboard/google/reef/variants/snappy/devicetree.cb
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@ -112,6 +112,12 @@ chip soc/intel/apollolake
# Minimum SLP S3 assertion width 28ms. # Minimum SLP S3 assertion width 28ms.
register "slp_s3_assertion_width_usecs" = "28000" register "slp_s3_assertion_width_usecs" = "28000"
# Override USB2 PER PORT register (PORT 1)
register "usb2eye[1]" = "{
.Usb20PerPortPeTxiSet = 7,
.Usb20PerPortTxiSet = 0,
}"
device domain 0 on device domain 0 on
device pci 00.0 on end # - Host Bridge device pci 00.0 on end # - Host Bridge
device pci 00.1 on end # - DPTF device pci 00.1 on end # - DPTF