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Save and restore F15TN graphics command register 

In the AGESA routine GfxInitSview() called in the S3save path,
the IO Space bit was getting cleared from the command register.
This kept seabios from initializing the video bios.  If the vbios
was loaded by coreboot, this routine was skipped, allowing seabios
to initialize vbios as well.  I have modified the routine to save
and restore the command register instead of clearing the IO Space
bit.

Change-Id: I756b0606adbc47da96780308c911852e39f547c7
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2172
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
This commit is contained in:
Martin Roth 2013-01-15 13:17:30 -07:00
parent eac220f8b5
commit e4cd00cacb
1 changed files with 3 additions and 1 deletions
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4
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSview/GnbSview.c
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@ -126,6 +126,7 @@ GfxInitSview (
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
GFX_PLATFORM_CONFIG *Gfx;
UINT32 OriginalCmdReg;
IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitSview Enter\n");
AgesaStatus = AGESA_SUCCESS;
Status = GfxLocateConfigData (StdHeader, &Gfx);
@ -138,6 +139,7 @@ GfxInitSview (
VbiosImageInfo.ImagePtr = NULL;
VbiosImageInfo.GfxPciAddress = Gfx->GfxPciAddress;
VbiosImageInfo.Flags = GFX_VBIOS_IMAGE_FLAG_SPECIAL_POST;
GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x4, AccessS3SaveWidth8, &OriginalCmdReg, StdHeader);
GnbLibPciRMW (Gfx->GfxPciAddress.AddressValue | 0x4, AccessS3SaveWidth8, 0xff, BIT1 | BIT2 | BIT0, StdHeader);
Status = AgesaGetVbiosImage (0, &VbiosImageInfo);
if (Status == AGESA_SUCCESS && VbiosImageInfo.ImagePtr != NULL) {
@ -146,7 +148,7 @@ GfxInitSview (
GfxFmDisableController (StdHeader);
AgesaStatus = AGESA_ERROR;
}
GnbLibPciRMW (Gfx->GfxPciAddress.AddressValue | 0x4, AccessS3SaveWidth8, 0xf8, BIT1 | BIT2, StdHeader);
GnbLibPciRMW (Gfx->GfxPciAddress.AddressValue | 0x4, AccessS3SaveWidth8, 0x00, OriginalCmdReg, StdHeader);
}
}
}