util/inteltool: Add support for mobile 5 chipset
Dump registers on mobile 5. Successfully tested on X201. Change-Id: I606371801d3ae6c96d3d404c9775c254bd0ffbc9 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/2993 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
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@ -888,6 +888,123 @@ int print_intel_core_msrs(void)
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{ 0x0600, "IA32_DS_AREA" },
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};
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static const msr_entry_t model20650_global_msrs[] = {
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{ 0x0000, "IA32_P5_MC_ADDR" },
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{ 0x0001, "IA32_P5_MC_TYPE" },
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{ 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" },
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{ 0x0017, "IA32_PLATFORM_ID" },
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{ 0x002a, "MSR_EBC_HARD_POWERON" },
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// WRITE ONLY { 0x0079, "IA32_BIOS_UPDT_TRIG" },
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{ 0x00ce, "IA32_MSR_PLATFORM_INFO" },
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{ 0x00e2, "IA32_MSR_PMG_CST_CONFIG" },
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{ 0x019c, "IA32_THERM_STATUS" },
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{ 0x019d, "MSR_THERM2_CTL" },
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{ 0x01a0, "IA32_MISC_ENABLE" },
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{ 0x0200, "IA32_MTRR_PHYSBASE0" },
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{ 0x0201, "IA32_MTRR_PHYSMASK0" },
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{ 0x0202, "IA32_MTRR_PHYSBASE1" },
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{ 0x0203, "IA32_MTRR_PHYSMASK1" },
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{ 0x0204, "IA32_MTRR_PHYSBASE2" },
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{ 0x0205, "IA32_MTRR_PHYSMASK2" },
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{ 0x0206, "IA32_MTRR_PHYSBASE3" },
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{ 0x0207, "IA32_MTRR_PHYSMASK3" },
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{ 0x0208, "IA32_MTRR_PHYSBASE4" },
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{ 0x0209, "IA32_MTRR_PHYSMASK4" },
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{ 0x020a, "IA32_MTRR_PHYSBASE5" },
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{ 0x020b, "IA32_MTRR_PHYSMASK5" },
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{ 0x020c, "IA32_MTRR_PHYSBASE6" },
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{ 0x020d, "IA32_MTRR_PHYSMASK6" },
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{ 0x020e, "IA32_MTRR_PHYSBASE7" },
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{ 0x020f, "IA32_MTRR_PHYSMASK7" },
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{ 0x0250, "IA32_MTRR_FIX64K_00000" },
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{ 0x0258, "IA32_MTRR_FIX16K_80000" },
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{ 0x0259, "IA32_MTRR_FIX16K_A0000" },
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{ 0x0268, "IA32_MTRR_FIX4K_C0000" },
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{ 0x0269, "IA32_MTRR_FIX4K_C8000" },
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{ 0x026a, "IA32_MTRR_FIX4K_D0000" },
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{ 0x026b, "IA32_MTRR_FIX4K_D8000" },
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{ 0x026c, "IA32_MTRR_FIX4K_E0000" },
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{ 0x026d, "IA32_MTRR_FIX4K_E8000" },
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{ 0x026e, "IA32_MTRR_FIX4K_F0000" },
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{ 0x026f, "IA32_MTRR_FIX4K_F8000" },
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{ 0x02ff, "IA32_MTRR_DEF_TYPE" },
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{ 0x0300, "MSR_BPU_COUNTER0" },
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{ 0x0301, "MSR_BPU_COUNTER1" },
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/* Skipped through 0x3ff for now*/
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/* All MCX_ADDR AND MCX_MISC MSRs depend on a bit being
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* set in MCX_STATUS */
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{ 0x400, "IA32_MC0_CTL" },
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{ 0x401, "IA32_MC0_STATUS" },
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{ 0x402, "IA32_MC0_ADDR" },
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{ 0x403, "IA32_MC0_MISC" },
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{ 0x404, "IA32_MC1_CTL" },
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{ 0x405, "IA32_MC1_STATUS" },
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{ 0x406, "IA32_MC1_ADDR" },
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{ 0x407, "IA32_MC1_MISC" },
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{ 0x408, "IA32_MC2_CTL" },
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{ 0x409, "IA32_MC2_STATUS" },
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{ 0x40a, "IA32_MC2_ADDR" },
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{ 0x40c, "IA32_MC3_CTL" },
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{ 0x40d, "IA32_MC3_STATUS" },
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{ 0x40e, "IA32_MC3_ADDR" },
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{ 0x410, "IA32_MC4_CTL" },
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{ 0x411, "IA32_MC4_STATUS" },
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};
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static const msr_entry_t model20650_per_core_msrs[] = {
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{ 0x0010, "IA32_TIME_STAMP_COUNTER" },
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{ 0x001b, "IA32_APIC_BASE" },
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{ 0x003a, "IA32_FEATURE_CONTROL" },
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{ 0x008b, "IA32_BIOS_SIGN_ID" },
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{ 0x009b, "IA32_SMM_MONITOR_CTL" },
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{ 0x00e4, "IA32_PMG_IO_CAPTURE_BASE" },
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{ 0x00fe, "IA32_MTRRCAP" },
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{ 0x0174, "IA32_SYSENTER_CS" },
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{ 0x0175, "IA32_SYSENTER_ESP" },
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{ 0x0176, "IA32_SYSENTER_EIP" },
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{ 0x0179, "IA32_MCG_CAP" },
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{ 0x017a, "IA32_MCG_STATUS" },
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{ 0x0186, "MSR_MCG_RBP" },
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{ 0x0187, "MSR_MCG_RSP" },
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{ 0x0188, "MSR_MCG_RFLAGS" },
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{ 0x0189, "MSR_MCG_RIP" },
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{ 0x0194, "MSR_MCG_R12" },
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{ 0x0198, "IA32_PERF_STATUS" },
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{ 0x0199, "IA32_PERF_CTL" },
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{ 0x019a, "IA32_CLOCK_MODULATION" },
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{ 0x019b, "IA32_THERM_INTERRUPT" },
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{ 0x01a0, "IA32_MISC_ENABLE" }, // Bit 34 is Core Specific
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{ 0x01aa, "IA32_MISC_PWR_MGMT" },
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{ 0x01d9, "MSR_DEBUGCTLA" },
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{ 0x01fc, "MSR_POWER_CTL" },
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{ 0x0277, "IA32_PAT" },
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/** Virtualization
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{ 0x480, "IA32_VMX_BASIC" },
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through
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{ 0x48b, "IA32_VMX_PROCBASED_CTLS2" },
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Not implemented in my CPU
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*/
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{ 0x0600, "IA32_DS_AREA" },
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/* 0x0680 - 0x06cf Branch Records Skipped */
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{ 0x3a, "IA32_FEATURE_CONTROL" },
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{ 0x13c, "MSR_FEATURE_CONFIG" },
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{ 0x194, "MSR_FLEX_RATIO" },
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{ 0x1a0, "IA32_MISC_ENABLE" },
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{ 0x1a2, "MSR_TEMPERATURE_TARGET" },
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{ 0x199, "IA32_PERF_CTL" },
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{ 0x19b, "IA32_THERM_INTERRUPT" },
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{ 0x401, "IA32_MC0_STATUS" },
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{ 0x2e, "MSR_PIC_MSG_CONTROL" },
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{ 0xce, "MSR_PLATFORM_INFO" },
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{ 0xe2, "MSR_PMG_CST_CONFIG_CONTROL" },
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{ 0xe4, "MSR_PMG_IO_CAPTURE_BASE" },
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{ 0x1aa, "MSR_MISC_PWR_MGMT" },
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{ 0x1ad, "MSR_TURBO_RATIO_LIMIT" },
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{ 0x1fc, "MSR_POWER_CTL" },
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};
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typedef struct {
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unsigned int model;
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const msr_entry_t *global_msrs;
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@ -904,6 +1021,7 @@ int print_intel_core_msrs(void)
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{ 0x00f20, modelf2x_global_msrs, ARRAY_SIZE(modelf2x_global_msrs), modelf2x_per_core_msrs, ARRAY_SIZE(modelf2x_per_core_msrs) },
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{ 0x00f40, modelf4x_global_msrs, ARRAY_SIZE(modelf4x_global_msrs), modelf4x_per_core_msrs, ARRAY_SIZE(modelf4x_per_core_msrs) },
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{ 0x106c0, model6_atom_global_msrs, ARRAY_SIZE(model6_atom_global_msrs), model6_atom_per_core_msrs, ARRAY_SIZE(model6_atom_per_core_msrs) },
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{ 0x20650, model20650_global_msrs, ARRAY_SIZE(model20650_global_msrs), model20650_per_core_msrs, ARRAY_SIZE(model20650_per_core_msrs) },
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};
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cpu_t *cpu = NULL;
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@ -523,6 +523,12 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
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size = ARRAY_SIZE(i631x_gpio_registers);
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break;
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case PCI_DEVICE_ID_INTEL_MOBILE_5:
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gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
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gpio_registers = i631x_gpio_registers;
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size = ARRAY_SIZE(i631x_gpio_registers);
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break;
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case PCI_DEVICE_ID_INTEL_82371XX:
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printf("This southbridge has GPIOs in the PM unit.\n");
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return 1;
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@ -60,6 +60,7 @@
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#define PCI_DEVICE_ID_INTEL_ICH9M 0x2919
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#define PCI_DEVICE_ID_INTEL_ICH9ME 0x2917
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#define PCI_DEVICE_ID_INTEL_ICH10R 0x3a16
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#define PCI_DEVICE_ID_INTEL_MOBILE_5 0x3b07
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#define PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC 0x8119
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#define PCI_DEVICE_ID_INTEL_Z68 0x1c44
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#define PCI_DEVICE_ID_INTEL_P67 0x1c46
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@ -64,13 +64,97 @@ static const io_register_t sandybridge_mch_registers[] = {
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{ 0x5D10, 8, "SSKPD" }, // Sticky Scratchpad Data
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};
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volatile uint8_t *mchbar;
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static void write_mchbar32 (uint32_t addr, uint32_t val)
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{
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* (volatile uint32_t *) (mchbar + addr) = val;
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}
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static uint32_t read_mchbar32 (uint32_t addr)
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{
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return * (volatile uint32_t *) (mchbar + addr);
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}
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static uint8_t read_mchbar8 (uint32_t addr)
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{
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return * (volatile uint8_t *) (mchbar + addr);
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}
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static u16 read_500 (int channel, u16 addr, int split)
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{
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uint32_t val;
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write_mchbar32 (0x500 + (channel << 10), 0);
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while (read_mchbar32 (0x500 + (channel << 10)) & 0x800000);
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write_mchbar32 (0x500 + (channel << 10), 0x80000000 | (((read_mchbar8 (0x246 + (channel << 10)) >> 2) & 3) + 0xb88 - addr));
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while (read_mchbar32 (0x500 + (channel << 10)) & 0x800000);
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val = read_mchbar32 (0x508 + (channel << 10));
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return val & ((1 << split) - 1);
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}
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static inline u16 get_lane_offset (int slot, int rank, int lane)
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{
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return 0x124 * lane + ((lane & 4) ? 0x23e : 0) + 11 * rank + 22 * slot - 0x452 * (lane == 8);
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}
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static inline u16 get_timing_register_addr (int lane, int tm, int slot, int rank)
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{
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const u16 offs[] = { 0x1d, 0xa8, 0xe6, 0x5c };
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return get_lane_offset (slot, rank, lane) + offs[(tm + 3) % 4];
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}
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static void write_1d0 (u32 val, u16 addr, int bits, int flag)
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{
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write_mchbar32 (0x1d0, 0);
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while (read_mchbar32 (0x1d0) & 0x800000);
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write_mchbar32 (0x1d4, (val & ((1 << bits) - 1)) | (2 << bits) | (flag << bits));
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write_mchbar32 (0x1d0, 0x40000000 | addr);
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while (read_mchbar32 (0x1d0) & 0x800000);
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}
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static u16 read_1d0 (u16 addr, int split)
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{
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u32 val;
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write_mchbar32 (0x1d0, 0);
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while (read_mchbar32 (0x1d0) & 0x800000);
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write_mchbar32 (0x1d0, 0x80000000 | (((read_mchbar8 (0x246) >> 2) & 3) + 0x361 - addr));
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while (read_mchbar32 (0x1d0) & 0x800000);
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val = read_mchbar32 (0x1d8);
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write_1d0 (0, 0x33d, 0, 0);
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write_1d0 (0, 0x33d, 0, 0);
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return val & ((1 << split) - 1);
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}
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static void dump_timings (void)
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{
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int channel, slot, rank, lane, i;
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printf ("Timings:\n");
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for (channel = 0; channel < 2; channel++)
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for (slot = 0; slot < 2; slot++)
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for (rank = 0; rank < 2; rank++) {
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printf ("channel %d, slot %d, rank %d\n", channel, slot, rank);
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for (lane = 0; lane < 9; lane++) {
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printf ("lane %d: ", lane);
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for (i = 0; i < 4; i++) {
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printf ("%x ", read_500 (channel,
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get_timing_register_addr (lane, i, slot, rank), 9));
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}
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printf ("\n");
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}
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}
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printf ("[178] = %x\n", read_1d0 (0x178, 7));
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printf ("[10b] = %x\n", read_1d0 (0x10b, 6));
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}
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/*
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* (G)MCH MMIO Config Space
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*/
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int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
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{
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int i, size = (16 * 1024);
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volatile uint8_t *mchbar;
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uint64_t mchbar_phys;
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const io_register_t *mch_registers = NULL;
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struct pci_dev *nb_device6; /* "overflow device" on i865 */
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@ -229,6 +313,10 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
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}
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}
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if (nb->device_id == PCI_DEVICE_ID_INTEL_CORE_1ST_GEN) {
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printf ("clock_speed_index = %x\n", read_500 (0,0x609, 6) >> 1);
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dump_timings ();
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}
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unmap_physical((void *)mchbar, size);
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return 0;
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}
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@ -761,6 +761,12 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc)
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size = ARRAY_SIZE(i63xx_pm_registers);
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break;
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case PCI_DEVICE_ID_INTEL_MOBILE_5:
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pmbase = pci_read_word(sb, 0x40) & 0xfffc;
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pm_registers = i63xx_pm_registers;
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size = ARRAY_SIZE(i63xx_pm_registers);
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break;
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case 0x1234: // Dummy for non-existent functionality
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printf("This southbridge does not have PMBASE.\n");
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return 1;
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@ -47,6 +47,7 @@ int print_rcba(struct pci_dev *sb)
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case PCI_DEVICE_ID_INTEL_ICH10R:
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case PCI_DEVICE_ID_INTEL_NM10:
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case PCI_DEVICE_ID_INTEL_I63XX:
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case PCI_DEVICE_ID_INTEL_MOBILE_5:
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case PCI_DEVICE_ID_INTEL_Z68:
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case PCI_DEVICE_ID_INTEL_P67:
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case PCI_DEVICE_ID_INTEL_UM67:
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