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coreboot-kgpe-d16
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fixes for tyan 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich 2004-03-12 15:13:38 +00:00
parent a40a17c50c
commit e4fc0ab250
31 changed files with 1017 additions and 600 deletions
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80
src/mainboard/tyan/s2880/Config.lb
View File

@ -1,6 +1,9 @@
uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses LB_CKS_RANGE_START
uses LB_CKS_RANGE_END
uses LB_CKS_LOC
uses MAINBOARD
uses ARCH
#
@ -13,29 +16,35 @@ uses ARCH
###
### Build the objects we have code for in this directory.
###
##object mainboard.o
config chip.h
register "fixup_scsi" = "1"
register "fixup_vga" = "1"
##
## Move the default LinuxBIOS cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default LB_CKS_LOC=123
driver mainboard.o
driver lsi_scsi.o
driver adaptec_scsi.o
driver promise_sata.o
driver intel_nic.o
#driver lsi_scsi.o
#driver adaptec_scsi.o
#driver promise_sata.o
#driver intel_nic.o
object reset.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
#
arch i386 end
#cpu k8 end
#
###
### Build our 16 bit and 32 bit linuxBIOS entry code
###
mainboardinit cpu/i386/entry16.inc
mainboardinit cpu/i386/entry32.inc
mainboardinit cpu/i386/bist32.inc
ldscript /cpu/i386/entry16.lds
ldscript /cpu/i386/entry32.lds
#
@ -87,28 +96,13 @@ end
###
### Setup the serial port
###
#mainboardinit superiowinbond/w83627hf/setup_serial.inc
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
#
####
#### O.k. We aren't just an intermediary anymore!
####
#
###
### When debugging disable the watchdog timer
###
##option MAXIMUM_CONSOLE_LOGLEVEL=7
#default MAXIMUM_CONSOLE_LOGLEVEL=7
#
#if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
mainboardinit cpu/i386/bist32_fail.inc
#
###
### Romcc output
###
#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
#mainboardinit .failover.inc
makerule ./failover.E
depends "$(MAINBOARD)/failover.c"
@ -120,8 +114,8 @@ makerule ./failover.inc
action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
depends "$(MAINBOARD)/auto.c option_table.h"
action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
end
makerule ./auto.inc
depends "./romcc ./auto.E"
@ -160,6 +154,31 @@ northbridge amd/amdk8 "mc0"
pci 1:0.1 on
pci 1:0.2 on
pci 1:1.0 off
superio winbond/w83627hf link 1
pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
pnp 2e.3 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
pnp 2e.6 off # CIR
pnp 2e.7 off # GAME_MIDI_GIPO1
pnp 2e.8 off # GPIO2
pnp 2e.9 off # GPIO3
pnp 2e.a off # ACPI
pnp 2e.b off # HW Monitor
end
end
end
@ -173,21 +192,8 @@ northbridge amd/amdk8 "mc1"
end
#northbridge amd/amdk8
#end
#southbridge amd/amd8111 "amd8111"
#end
#southbridge amd/amd8131 "amd8131"
#end
#mainboardinit archi386/smp/secondary.inc
#superio NSC/pc87360
# register "com1" = "{1}"
# register "lpt" = "{1}"
#end
dir /pc80
##dir /src/superio/winbond/w83627hf
#dir /bioscall
#dir /cpu/k8
cpu k8 "cpu0"
register "up" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
end

95
src/mainboard/tyan/s2880/auto.c
View File

@ -1,13 +1,17 @@
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <cpu/p6/apic.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/smp/lapic.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include "northbridge/amd/amdk8/early_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/k8/apic_timer.c"
@ -16,8 +20,25 @@
#include "northbridge/amd/amdk8/reset_test.c"
#include "debug.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static void hard_reset(void)
{
set_bios_reset();
/* enable cf9 */
pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
/* reset */
outb(0x0e, 0x0cf9);
}
static void soft_reset(void)
{
set_bios_reset();
pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
}
#define REV_B_RESET 0
static void memreset_setup(void)
{
@ -95,45 +116,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
/* include mainboard specific ht code */
#include "hypertransport.c"
//#include "northbridge/amd/amdk8/cpu_ldtstop.c"
//#include "southbridge/amd/amd8111/amd8111_ldtstop.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
static void enable_lapic(void)
{
msr_t msr;
msr = rdmsr(0x1b);
msr.hi &= 0xffffff00;
msr.lo &= 0x000007ff;
msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
wrmsr(0x1b, msr);
}
static void stop_this_cpu(void)
{
unsigned apicid;
apicid = apic_read(APIC_ID) >> 24;
/* Send an APIC INIT to myself */
apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
/* Wait for the ipi send to finish */
apic_wait_icr_idle();
/* Deassert the APIC INIT */
apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
/* Wait for the ipi send to finish */
apic_wait_icr_idle();
/* If I haven't halted spin forever */
for(;;) {
hlt();
}
}
#define FIRST_CPU 1
#define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
@ -163,21 +149,26 @@ static void main(void)
},
#endif
};
if (cpu_init_detected()) {
asm("jmp __cpu_reset");
}
enable_lapic();
init_timer();
if (!boot_cpu() ) {
// notify_bsp_ap_is_stopped();
stop_this_cpu();
}
uart_init();
console_init();
setup_default_resource_map();
setup_coherent_ht_domain();
enumerate_ht_chain(0);
distinguish_cpu_resets(0);
int needs_reset;
enable_lapic();
init_timer();
if (cpu_init_detected()) {
asm("jmp __cpu_reset");
}
distinguish_cpu_resets();
if (!boot_cpu()) {
stop_this_cpu();
}
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
setup_default_resource_map();
needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
if (needs_reset) {
print_info("ht reset -");
soft_reset();
}
#if 0
print_pci_devices();

26
src/mainboard/tyan/s2880/cmos.layout
View File

@ -29,6 +29,9 @@ entries
386 1 e 1 ECC_memory
388 4 r 0 reboot_bits
392 3 e 5 baud_rate
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
416 4 e 7 boot_first
@ -36,7 +39,14 @@ entries
424 4 e 7 boot_third
428 4 h 0 boot_index
432 8 h 0 boot_countdown
1008 16 h 0 check_sum
440 4 e 9 slow_cpu
444 1 e 1 nmi
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory
enumerations
@ -66,9 +76,21 @@ enumerations
7 9 Fallback_HDD
7 10 Fallback_Floppy
#7 3 ROM
8 0 200Mhz
8 1 166Mhz
8 2 133Mhz
8 3 100Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
checksums
checksum 392 1007 1008
checksum 392 983 984

68
src/mainboard/tyan/s2880/failover.c
View File

@ -3,36 +3,78 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include "arch/romcc_io.h"
#include <arch/romcc_io.h>
#include <arch/smp/lapic.h>
#include "pc80/mc146818rtc_early.c"
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
#include "cpu/p6/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#define HAVE_REGPARM_SUPPORT 0
#if HAVE_REGPARM_SUPPORT
static unsigned long main(unsigned long bist)
{
#else
static void main(void)
{
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain(0);
unsigned long bist = 0;
#endif
/* Make cerain my local apic is useable */
enable_lapic();
/* Setup the 8111 */
amd8111_enable_rom();
/* Is this a cpu reset? */
/* Is this a cpu only reset? */
if (cpu_init_detected()) {
if (last_boot_normal()) {
asm("jmp __normal_image");
goto normal_image;
} else {
asm("jmp __cpu_reset");
goto cpu_reset;
}
}
/* Is this a secondary cpu? */
else if (!boot_cpu() && last_boot_normal()) {
asm("jmp __normal_image");
if (!boot_cpu()) {
if (last_boot_normal()) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Setup the 8111 */
amd8111_enable_rom();
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
asm("jmp __normal_image");
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
asm("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
asm("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
fallback_image:
#if HAVE_REGPARM_SUPPORT
return bist;
#else
return;
#endif
}

73
src/mainboard/tyan/s2881/Config.lb
View File

@ -1,6 +1,9 @@
uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses LB_CKS_RANGE_START
uses LB_CKS_RANGE_END
uses LB_CKS_LOC
uses MAINBOARD
uses ARCH
#
@ -19,10 +22,19 @@ register "fixup_scsi" = "1"
register "fixup_vga" = "1"
##
## Move the default LinuxBIOS cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default LB_CKS_LOC=123
driver mainboard.o
driver adaptec_scsi.o
driver si_sata.o
driver intel_nic.o
#driver adaptec_scsi.o
#driver si_sata.o
#driver intel_nic.o
#driver broadcom_nic.o
object reset.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
@ -35,6 +47,7 @@ arch i386 end
###
mainboardinit cpu/i386/entry16.inc
mainboardinit cpu/i386/entry32.inc
mainboardinit cpu/i386/bist32.inc
ldscript /cpu/i386/entry16.lds
ldscript /cpu/i386/entry32.lds
#
@ -86,23 +99,15 @@ end
###
### Setup the serial port
###
#mainboardinit superiowinbond/w83627hf/setup_serial.inc
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
mainboardinit cpu/i386/bist32_fail.inc
#
####
#### O.k. We aren't just an intermediary anymore!
####
#
###
### When debugging disable the watchdog timer
###
##option MAXIMUM_CONSOLE_LOGLEVEL=7
#default MAXIMUM_CONSOLE_LOGLEVEL=7
#
#if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
#
###
### Romcc output
###
#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
@ -118,9 +123,9 @@ makerule ./failover.inc
depends "./romcc ./failover.E"
action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h"
action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
end
makerule ./auto.inc
depends "./romcc ./auto.E"
@ -159,6 +164,31 @@ northbridge amd/amdk8 "mc0"
pci 1:0.1 on
pci 1:0.2 on
pci 1:1.0 off
superio winbond/w83627hf link 1
pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
pnp 2e.3 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
pnp 2e.6 off # CIR
pnp 2e.7 off # GAME_MIDI_GIPO1
pnp 2e.8 off # GPIO2
pnp 2e.9 off # GPIO3
pnp 2e.a off # ACPI
pnp 2e.b off # HW Monitor
end
end
end
@ -172,21 +202,8 @@ northbridge amd/amdk8 "mc1"
end
#northbridge amd/amdk8
#end
#southbridge amd/amd8111 "amd8111"
#end
#southbridge amd/amd8131 "amd8131"
#end
#mainboardinit archi386/smp/secondary.inc
#superio NSC/pc87360
# register "com1" = "{1}"
# register "lpt" = "{1}"
#end
dir /pc80
##dir /src/superio/winbond/w83627hf
#dir /bioscall
#dir /cpu/k8
cpu k8 "cpu0"
register "up" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
end

97
src/mainboard/tyan/s2881/auto.c
View File

@ -1,13 +1,16 @@
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <cpu/p6/apic.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/smp/lapic.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include "northbridge/amd/amdk8/early_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/k8/apic_timer.c"
@ -16,7 +19,25 @@
#include "northbridge/amd/amdk8/reset_test.c"
#include "debug.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static void hard_reset(void)
{
set_bios_reset();
/* enable cf9 */
pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
/* reset */
outb(0x0e, 0x0cf9);
}
static void soft_reset(void)
{
set_bios_reset();
pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
}
#define REV_B_RESET 0
static void memreset_setup(void)
@ -95,47 +116,12 @@ static inline int spd_read_byte(unsigned device, unsigned address)
/* include mainboard specific ht code */
#include "hypertransport.c"
//#include "northbridge/amd/amdk8/cpu_ldtstop.c"
//#include "southbridge/amd/amd8111/amd8111_ldtstop.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
#include "resourcemap.c" /* tyan does not want the default */
static void enable_lapic(void)
{
msr_t msr;
msr = rdmsr(0x1b);
msr.hi &= 0xffffff00;
msr.lo &= 0x000007ff;
msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
wrmsr(0x1b, msr);
}
static void stop_this_cpu(void)
{
unsigned apicid;
apicid = apic_read(APIC_ID) >> 24;
/* Send an APIC INIT to myself */
apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
/* Wait for the ipi send to finish */
apic_wait_icr_idle();
/* Deassert the APIC INIT */
apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
/* Wait for the ipi send to finish */
apic_wait_icr_idle();
/* If I haven't halted spin forever */
for(;;) {
hlt();
}
}
#define FIRST_CPU 1
#define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
@ -165,21 +151,26 @@ static void main(void)
},
#endif
};
if (cpu_init_detected()) {
asm("jmp __cpu_reset");
}
enable_lapic();
init_timer();
if (!boot_cpu() ) {
notify_bsp_ap_is_stopped();
stop_this_cpu();
}
uart_init();
console_init();
setup_s2881_resource_map();
setup_coherent_ht_domain();
enumerate_ht_chain(0);
distinguish_cpu_resets(0);
int needs_reset;
enable_lapic();
init_timer();
if (cpu_init_detected()) {
asm("jmp __cpu_reset");
}
distinguish_cpu_resets();
if (!boot_cpu()) {
stop_this_cpu();
}
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
setup_s2881_resource_map();
needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
if (needs_reset) {
print_info("ht reset -");
soft_reset();
}
#if 0
print_pci_devices();

26
src/mainboard/tyan/s2881/cmos.layout
View File

@ -29,6 +29,9 @@ entries
386 1 e 1 ECC_memory
388 4 r 0 reboot_bits
392 3 e 5 baud_rate
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
416 4 e 7 boot_first
@ -36,7 +39,14 @@ entries
424 4 e 7 boot_third
428 4 h 0 boot_index
432 8 h 0 boot_countdown
1008 16 h 0 check_sum
440 4 e 9 slow_cpu
444 1 e 1 nmi
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory
enumerations
@ -66,9 +76,21 @@ enumerations
7 9 Fallback_HDD
7 10 Fallback_Floppy
#7 3 ROM
8 0 200Mhz
8 1 166Mhz
8 2 133Mhz
8 3 100Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
checksums
checksum 392 1007 1008
checksum 392 983 984

68
src/mainboard/tyan/s2881/failover.c
View File

@ -3,36 +3,78 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include "arch/romcc_io.h"
#include <arch/romcc_io.h>
#include <arch/smp/lapic.h>
#include "pc80/mc146818rtc_early.c"
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
#include "cpu/p6/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#define HAVE_REGPARM_SUPPORT 0
#if HAVE_REGPARM_SUPPORT
static unsigned long main(unsigned long bist)
{
#else
static void main(void)
{
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain(0);
unsigned long bist = 0;
#endif
/* Make cerain my local apic is useable */
enable_lapic();
/* Setup the 8111 */
amd8111_enable_rom();
/* Is this a cpu reset? */
/* Is this a cpu only reset? */
if (cpu_init_detected()) {
if (last_boot_normal()) {
asm("jmp __normal_image");
goto normal_image;
} else {
asm("jmp __cpu_reset");
goto cpu_reset;
}
}
/* Is this a secondary cpu? */
else if (!boot_cpu() && last_boot_normal()) {
asm("jmp __normal_image");
if (!boot_cpu()) {
if (last_boot_normal()) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Setup the 8111 */
amd8111_enable_rom();
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
asm("jmp __normal_image");
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
asm("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
asm("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
fallback_image:
#if HAVE_REGPARM_SUPPORT
return bist;
#else
return;
#endif
}

60
src/mainboard/tyan/s2882/Config.lb
View File

@ -1,6 +1,9 @@
uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses LB_CKS_RANGE_START
uses LB_CKS_RANGE_END
uses LB_CKS_LOC
uses MAINBOARD
uses ARCH
#
@ -19,10 +22,18 @@ register "fixup_scsi" = "1"
register "fixup_vga" = "1"
##
## Move the default LinuxBIOS cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default LB_CKS_LOC=123
driver mainboard.o
driver adaptec_scsi.o
driver si_sata.o
#driver adaptec_scsi.o
#driver si_sata.o
driver intel_nic.o
#driver broadcom_nic.o
object reset.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
@ -35,6 +46,7 @@ arch i386 end
###
mainboardinit cpu/i386/entry16.inc
mainboardinit cpu/i386/entry32.inc
mainboardinit cpu/i386/bist32.inc
ldscript /cpu/i386/entry16.lds
ldscript /cpu/i386/entry32.lds
#
@ -86,9 +98,9 @@ end
###
### Setup the serial port
###
#mainboardinit superiowinbond/w83627hf/setup_serial.inc
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
mainboardinit cpu/i386/bist32_fail.inc
#
####
#### O.k. We aren't just an intermediary anymore!
@ -119,8 +131,8 @@ makerule ./failover.inc
action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
depends "$(MAINBOARD)/auto.c option_table.h"
action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
end
makerule ./auto.inc
depends "./romcc ./auto.E"
@ -159,6 +171,31 @@ northbridge amd/amdk8 "mc0"
pci 1:0.1 on
pci 1:0.2 on
pci 1:1.0 off
superio winbond/w83627hf link 1
pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
pnp 2e.3 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
pnp 2e.6 off # CIR
pnp 2e.7 off # GAME_MIDI_GIPO1
pnp 2e.8 off # GPIO2
pnp 2e.9 off # GPIO3
pnp 2e.a off # ACPI
pnp 2e.b off # HW Monitor
end
end
end
@ -171,21 +208,8 @@ northbridge amd/amdk8 "mc1"
pci 0:19.3
end
#northbridge amd/amdk8
#end
#southbridge amd/amd8111 "amd8111"
#end
#southbridge amd/amd8131 "amd8131"
#end
#mainboardinit archi386/smp/secondary.inc
#superio NSC/pc87360
# register "com1" = "{1}"
# register "lpt" = "{1}"
#end
dir /pc80
##dir /src/superio/winbond/w83627hf
#dir /bioscall
#dir /cpu/k8
cpu k8 "cpu0"
register "up" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
end

104
src/mainboard/tyan/s2882/auto.c
View File

@ -1,21 +1,43 @@
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <cpu/p6/apic.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/smp/lapic.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include "northbridge/amd/amdk8/early_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/k8/apic_timer.c"
#include "lib/delay.c"
#include "cpu/p6/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "debug.c"
#include "debug.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static void hard_reset(void)
{
set_bios_reset();
/* enable cf9 */
pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
/* reset */
outb(0x0e, 0x0cf9);
}
static void soft_reset(void)
{
set_bios_reset();
pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
}
#define REV_B_RESET 0
static void memreset_setup(void)
@ -95,45 +117,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
/* include mainboard specific ht code */
#include "hypertransport.c"
//#include "northbridge/amd/amdk8/cpu_ldtstop.c"
//#include "southbridge/amd/amd8111/amd8111_ldtstop.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
static void enable_lapic(void)
{
msr_t msr;
msr = rdmsr(0x1b);
msr.hi &= 0xffffff00;
msr.lo &= 0x000007ff;
msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
wrmsr(0x1b, msr);
}
static void stop_this_cpu(void)
{
unsigned apicid;
apicid = apic_read(APIC_ID) >> 24;
/* Send an APIC INIT to myself */
apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
/* Wait for the ipi send to finish */
apic_wait_icr_idle();
/* Deassert the APIC INIT */
apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
/* Wait for the ipi send to finish */
apic_wait_icr_idle();
/* If I haven't halted spin forever */
for(;;) {
hlt();
}
}
#define FIRST_CPU 1
#define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
@ -167,29 +154,36 @@ static void main(void)
},
#endif
};
if (cpu_init_detected()) {
asm("jmp __cpu_reset");
}
enable_lapic();
init_timer();
if (!boot_cpu() ) {
notify_bsp_ap_is_stopped();
stop_this_cpu();
}
uart_init();
console_init();
setup_default_resource_map();
setup_coherent_ht_domain();
enumerate_ht_chain(0);
distinguish_cpu_resets(0);
int needs_reset;
enable_lapic();
init_timer();
if (cpu_init_detected()) {
asm("jmp __cpu_reset");
}
distinguish_cpu_resets();
if (!boot_cpu()) {
stop_this_cpu();
}
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
setup_default_resource_map();
needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
if (needs_reset) {
print_info("ht reset -");
soft_reset();
}
#if 0
print_pci_devices();
#endif
enable_smbus();
#if 0
dump_spd_registers(&cpu[0]);
// dump_spd_registers(&cpu[0]);
dump_smbus_registers();
#endif
memreset_setup();
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);

26
src/mainboard/tyan/s2882/cmos.layout
View File

@ -29,6 +29,9 @@ entries
386 1 e 1 ECC_memory
388 4 r 0 reboot_bits
392 3 e 5 baud_rate
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
416 4 e 7 boot_first
@ -36,7 +39,14 @@ entries
424 4 e 7 boot_third
428 4 h 0 boot_index
432 8 h 0 boot_countdown
1008 16 h 0 check_sum
440 4 e 9 slow_cpu
444 1 e 1 nmi
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory
enumerations
@ -66,9 +76,21 @@ enumerations
7 9 Fallback_HDD
7 10 Fallback_Floppy
#7 3 ROM
8 0 200Mhz
8 1 166Mhz
8 2 133Mhz
8 3 100Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
checksums
checksum 392 1007 1008
checksum 392 983 984

74
src/mainboard/tyan/s2882/failover.c
View File

@ -3,44 +3,78 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include "arch/romcc_io.h"
#include <arch/romcc_io.h>
#include <arch/smp/lapic.h>
#include "pc80/mc146818rtc_early.c"
#if 0
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#endif
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
#include "cpu/p6/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#define HAVE_REGPARM_SUPPORT 0
#if HAVE_REGPARM_SUPPORT
static unsigned long main(unsigned long bist)
{
#else
static void main(void)
{
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
#if 0
uart_init();
console_init();
unsigned long bist = 0;
#endif
enumerate_ht_chain(0);
/* Make cerain my local apic is useable */
enable_lapic();
/* Setup the 8111 */
amd8111_enable_rom();
/* Is this a cpu reset? */
/* Is this a cpu only reset? */
if (cpu_init_detected()) {
if (last_boot_normal()) {
asm("jmp __normal_image");
goto normal_image;
} else {
asm("jmp __cpu_reset");
goto cpu_reset;
}
}
/* Is this a secondary cpu? */
else if (!boot_cpu() && last_boot_normal()) {
asm("jmp __normal_image");
if (!boot_cpu()) {
if (last_boot_normal()) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Setup the 8111 */
amd8111_enable_rom();
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
asm("jmp __normal_image");
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
asm("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
asm("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
fallback_image:
#if HAVE_REGPARM_SUPPORT
return bist;
#else
return;
#endif
}

26
src/mainboard/tyan/s2882/irq_tables.c
View File

@ -22,18 +22,18 @@ const struct irq_routing_table intel_irq_routing_table = {
{
{1,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
{0x4,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0},
{0x4,0x30, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
{0x3,0x18, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
{0x3,0x8, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0},
{0x2,0x18, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0},
{0x2,0x10, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
{0x4,0x20, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0},
{0x4,0x28, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
{0x4,0x40, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
{0x2,0x30, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
{0x3,0x20, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x6, 0},
{0x3,0x28, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x7, 0},
{0x2,0x28, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
{0x2,0x48, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
{0x4,(6<<3)|0, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
{0x3,(3<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
{0x3,(1<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0},
{0x2,(3<<3)|0, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0},
{0x2,(2<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
{0x4,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0},
{0x4,(5<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
{0x4,(8<<3)|0, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
{0x2,(6<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
{0x2,(5<<3)|0, {{0x3, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}}, 0, 0},
{0x2,(9<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
{0x3,(4<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x6, 0},
{0x3,(5<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x7, 0},
}
};

6
src/mainboard/tyan/s2882/mainboard.c
View File

@ -38,7 +38,7 @@ static void fixup_lsi_53c1030(struct device *pdev)
}
#endif
//extern static void lsi_scsi_init(struct device *dev);
#if 1
#if 0
static void print_pci_regs(struct device *dev)
{
uint8_t byte;
@ -92,8 +92,8 @@ static void onboard_scsi_fixup(void)
{
struct device *dev;
unsigned char i,j,k;
#if 0
for(i=0;i<=4;i++) {
#if 0
for(i=0;i<=5;i++) {
for(j=0;j<=0x1f;j++) {
for (k=0;k<=6;k++){
dev = dev_find_slot(i, PCI_DEVFN(j, k));

151
src/mainboard/tyan/s2882/mptable.c
View File

@ -11,6 +11,12 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
static const char productid[12] = "S2882 ";
struct mp_config_table *mc;
unsigned char bus_num;
unsigned char bus_isa;
unsigned char bus_8131_1;
unsigned char bus_8131_2;
unsigned char bus_8111_1;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
memset(mc, 0, sizeof(*mc));
@ -29,15 +35,53 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
mc->reserved = 0;
smp_write_processors(mc, processor_map);
{
device_t dev;
/* 8111 */
dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
if (dev) {
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
}
else {
printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
bus_8111_1 = 4;
bus_isa = 5;
}
/* 8131-1 */
dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
if (dev) {
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
bus_8131_1 = 2;
}
/* 8131-2 */
dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
if (dev) {
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
bus_8131_2 = 3;
}
}
/*Bus: Bus ID Type*/
/* define bus and isa numbers */
for(bus_num = 0; bus_num < bus_isa; bus_num++) {
smp_write_bus(mc, bus_num, "PCI ");
}
smp_write_bus(mc, bus_isa, "ISA ");
/*Bus: Bus ID Type*/
smp_write_bus(mc, 0, "PCI ");
smp_write_bus(mc, 1, "PCI ");
smp_write_bus(mc, 2, "PCI ");
smp_write_bus(mc, 3, "PCI ");
smp_write_bus(mc, 4, "PCI ");
smp_write_bus(mc, 5, "ISA ");
/*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
{
@ -57,72 +101,77 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
}
}
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x0, 0x2, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x1, 0x2, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x0, 0x2, 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x3, 0x2, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x4, 0x2, 0x4);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x6, 0x2, 0x6);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x7, 0x2, 0x7);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x8, 0x2, 0x8);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0xc, 0x2, 0xc);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0xd, 0x2, 0xd);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0xe, 0x2, 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0xf, 0x2, 0xf);
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, 0x2, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, 0x2, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, 0x2, 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, 0x2, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, 0x2, 0x4);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, 0x2, 0x6);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, 0x2, 0x7);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, 0x2, 0x8);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, 0x2, 0xc);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, 0x2, 0xd);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, 0x2, 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, 0x2, 0xf);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, (4<<2)|3, 0x2, 0x13);
//On Board AMD USB
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x3, 0x2, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, 0x2, 0x13);
//On Board ATI Display Adapter
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x18, 0x2, 0x12);
#if 0
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (6<<2)|0, 0x2, 0x12);
#if 1
//Slot 5 PCI 32
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x10, 0x2, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x11, 0x2, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x12, 0x2, 0x12); //
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x13, 0x2, 0x13); //
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|0, 0x2, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|1, 0x2, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|2, 0x2, 0x12); //
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|3, 0x2, 0x13); //
#endif
//Onboard SI Serial ATA
// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x14, 0x2, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, 0x2, 0x13);
//Onboard Intel 82551 10/100M NIC
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (8<<2)|0, 0x2, 0x12);
#if 1
//Slot 3 PCIX 100/66
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x20, 0x3, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x21, 0x3, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x22, 0x3, 0x1);//
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x23, 0x3, 0x2);//
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|0, 0x3, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|1, 0x3, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|2, 0x3, 0x1);//
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|3, 0x3, 0x2);//
//Slot 4 PCIX 100/66
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x1c, 0x3, 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x1d, 0x3, 0x3);//
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x1e, 0x3, 0x0);//
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x1f, 0x3, 0x1);//
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|0, 0x3, 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|1, 0x3, 0x3);//
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|2, 0x3, 0x0);//
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|3, 0x3, 0x1);//
#endif
//Onboard adaptec scsi
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x18, 0x3, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x19, 0x3, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (6<<2)|0, 0x3, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (6<<2)|1, 0x3, 0x1);
//On Board NIC
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x24, 0x3, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x25, 0x3, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, 0x3, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|1, 0x3, 0x1);
#if 1
//Slot 1 PCI-X 133/100/66
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0xc, 0x4, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0xd, 0x4, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0xe, 0x4, 0x2); //
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0xf, 0x4, 0x3); //
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, 0x4, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|1, 0x4, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, 0x4, 0x2); //
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, 0x4, 0x3); //
//Slot 2 PCI-X 133/100/66
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x18, 0x4, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x19, 0x4, 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x1a, 0x4, 0x3);//
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x1b, 0x4, 0x0);//
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|0, 0x4, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|1, 0x4, 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|2, 0x4, 0x3);//
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|3, 0x4, 0x0);//
#endif
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x0);
smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x1);
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */

80
src/mainboard/tyan/s2885/Config.lb
View File

@ -1,6 +1,9 @@
uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses LB_CKS_RANGE_START
uses LB_CKS_RANGE_END
uses LB_CKS_LOC
uses MAINBOARD
uses ARCH
#
@ -18,12 +21,20 @@ config chip.h
register "fixup_scsi" = "1"
register "fixup_vga" = "1"
##
## Move the default LinuxBIOS cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default LB_CKS_LOC=123
driver mainboard.o
driver broadcom_nic.o
driver ti_firewire.o
driver adaptec_scsi.o
driver si_sata.o
driver intel_nic.o
#driver broadcom_nic.o
#driver ti_firewire.o
#driver adaptec_scsi.o
#driver si_sata.o
#driver intel_nic.o
object reset.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
@ -36,6 +47,7 @@ arch i386 end
###
mainboardinit cpu/i386/entry16.inc
mainboardinit cpu/i386/entry32.inc
mainboardinit cpu/i386/bist32.inc
ldscript /cpu/i386/entry16.lds
ldscript /cpu/i386/entry32.lds
#
@ -87,22 +99,13 @@ end
###
### Setup the serial port
###
#mainboardinit superiowinbond/w83627hf/setup_serial.inc
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
mainboardinit cpu/i386/bist32_fail.inc
#
####
#### O.k. We aren't just an intermediary anymore!
####
#
###
### When debugging disable the watchdog timer
###
##option MAXIMUM_CONSOLE_LOGLEVEL=7
#default MAXIMUM_CONSOLE_LOGLEVEL=7
#
#if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
#
###
### Romcc output
###
@ -120,8 +123,8 @@ makerule ./failover.inc
action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
depends "$(MAINBOARD)/auto.c option_table.h"
action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
end
makerule ./auto.inc
depends "./romcc ./auto.E"
@ -160,7 +163,31 @@ northbridge amd/amdk8 "mc0"
pci 1:0.1 on
pci 1:0.2 on
pci 1:1.0 off
superio winbond/w83627hf link 1
pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
pnp 2e.3 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
pnp 2e.6 off # CIR
pnp 2e.7 off # GAME_MIDI_GIPO1
pnp 2e.8 off # GPIO2
pnp 2e.9 off # GPIO3
pnp 2e.a off # ACPI
pnp 2e.b off # HW Monitor
end
end
southbridge amd/amd8151 "amd8151" link 0
pci 0:0.0
@ -177,24 +204,9 @@ northbridge amd/amdk8 "mc1"
pci 0:19.3
end
#northbridge amd/amdk8
#end
#southbridge amd/amd8111 "amd8111"
#end
#southbridge amd/amd8131 "amd8131"
#end
#southbridge amd/amd8151 "amd8151"
#end
#mainboardinit archi386/smp/secondary.inc
#superio NSC/pc87360
# register "com1" = "{1}"
# register "lpt" = "{1}"
#end
dir /pc80
##dir /src/superio/winbond/w83627hf
#dir /bioscall
#dir /cpu/k8
cpu k8 "cpu0"
register "up" = "{.chip = &amd8151, .ht_width=16, .ht_speed=600}"
register "down" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"

94
src/mainboard/tyan/s2885/auto.c
View File

@ -2,13 +2,16 @@
#include <stdint.h>
#include <device/pci_def.h>
#include <cpu/p6/apic.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/smp/lapic.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include "northbridge/amd/amdk8/early_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/k8/apic_timer.c"
@ -17,7 +20,25 @@
#include "northbridge/amd/amdk8/reset_test.c"
#include "debug.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static void hard_reset(void)
{
set_bios_reset();
/* enable cf9 */
pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
/* reset */
outb(0x0e, 0x0cf9);
}
static void soft_reset(void)
{
set_bios_reset();
pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
}
#define REV_B_RESET 0
static void memreset_setup(void)
@ -102,38 +123,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "resourcemap.c" /* tyan does not want the default */
static void enable_lapic(void)
{
msr_t msr;
msr = rdmsr(0x1b);
msr.hi &= 0xffffff00;
msr.lo &= 0x000007ff;
msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
wrmsr(0x1b, msr);
}
static void stop_this_cpu(void)
{
unsigned apicid;
apicid = apic_read(APIC_ID) >> 24;
/* Send an APIC INIT to myself */
apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
/* Wait for the ipi send to finish */
apic_wait_icr_idle();
/* Deassert the APIC INIT */
apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
/* Wait for the ipi send to finish */
apic_wait_icr_idle();
/* If I haven't halted spin forever */
for(;;) {
hlt();
}
}
#define FIRST_CPU 1
#define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
@ -163,22 +152,27 @@ static void main(void)
},
#endif
};
if (cpu_init_detected()) {
asm("jmp __cpu_reset");
}
enable_lapic();
init_timer();
if (!boot_cpu() ) {
// notify_bsp_ap_is_stopped();
stop_this_cpu();
}
uart_init();
console_init();
setup_s2885_resource_map();
setup_coherent_ht_domain();
enumerate_ht_chain(0);
distinguish_cpu_resets(0);
int needs_reset;
enable_lapic();
init_timer();
if (cpu_init_detected()) {
asm("jmp __cpu_reset");
}
distinguish_cpu_resets();
if (!boot_cpu()) {
stop_this_cpu();
}
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
setup_s2885_resource_map();
needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
if (needs_reset) {
print_info("ht reset -");
soft_reset();
}
#if 0
print_pci_devices();
#endif

26
src/mainboard/tyan/s2885/cmos.layout
View File

@ -29,6 +29,9 @@ entries
386 1 e 1 ECC_memory
388 4 r 0 reboot_bits
392 3 e 5 baud_rate
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
416 4 e 7 boot_first
@ -36,7 +39,14 @@ entries
424 4 e 7 boot_third
428 4 h 0 boot_index
432 8 h 0 boot_countdown
1008 16 h 0 check_sum
440 4 e 9 slow_cpu
444 1 e 1 nmi
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory
enumerations
@ -66,9 +76,21 @@ enumerations
7 9 Fallback_HDD
7 10 Fallback_Floppy
#7 3 ROM
8 0 200Mhz
8 1 166Mhz
8 2 133Mhz
8 3 100Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
checksums
checksum 392 1007 1008
checksum 392 983 984

74
src/mainboard/tyan/s2885/failover.c
View File

@ -3,44 +3,78 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include "arch/romcc_io.h"
#include <arch/romcc_io.h>
#include <arch/smp/lapic.h>
#include "pc80/mc146818rtc_early.c"
#if 0
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#endif
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
#include "cpu/p6/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#define HAVE_REGPARM_SUPPORT 0
#if HAVE_REGPARM_SUPPORT
static unsigned long main(unsigned long bist)
{
#else
static void main(void)
{
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
#if 0
uart_init();
console_init();
unsigned long bist = 0;
#endif
enumerate_ht_chain(0);
/* Make cerain my local apic is useable */
enable_lapic();
/* Setup the 8111 */
amd8111_enable_rom();
/* Is this a cpu reset? */
/* Is this a cpu only reset? */
if (cpu_init_detected()) {
if (last_boot_normal()) {
asm("jmp __normal_image");
goto normal_image;
} else {
asm("jmp __cpu_reset");
goto cpu_reset;
}
}
/* Is this a secondary cpu? */
else if (!boot_cpu() && last_boot_normal()) {
asm("jmp __normal_image");
if (!boot_cpu()) {
if (last_boot_normal()) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Setup the 8111 */
amd8111_enable_rom();
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
asm("jmp __normal_image");
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
asm("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
asm("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
fallback_image:
#if HAVE_REGPARM_SUPPORT
return bist;
#else
return;
#endif
}

68
src/mainboard/tyan/s4880/Config.lb
View File

@ -1,6 +1,9 @@
uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses LB_CKS_RANGE_START
uses LB_CKS_RANGE_END
uses LB_CKS_LOC
uses MAINBOARD
uses ARCH
#
@ -19,10 +22,17 @@ register "fixup_scsi" = "1"
#register "fixup_vga" = "1"
##
## Move the default LinuxBIOS cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default LB_CKS_LOC=123
driver mainboard.o
driver lsi_scsi.o
#driver lsi_scsi.o
#driver adaptec_scsi.o
driver si_sata.o
#driver si_sata.o
#driver intel_nic.o
object reset.o
if HAVE_MP_TABLE object mptable.o end
@ -36,6 +46,7 @@ arch i386 end
###
mainboardinit cpu/i386/entry16.inc
mainboardinit cpu/i386/entry32.inc
mainboardinit cpu/i386/bist32.inc
ldscript /cpu/i386/entry16.lds
ldscript /cpu/i386/entry32.lds
#
@ -87,23 +98,15 @@ end
###
### Setup the serial port
###
#mainboardinit superiowinbond/w83627hf/setup_serial.inc
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
mainboardinit cpu/i386/bist32_fail.inc
#
####
#### O.k. We aren't just an intermediary anymore!
####
#
###
### When debugging disable the watchdog timer
###
##option MAXIMUM_CONSOLE_LOGLEVEL=7
#default MAXIMUM_CONSOLE_LOGLEVEL=7
#
#if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
#
###
### Romcc output
###
#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
@ -120,8 +123,8 @@ makerule ./failover.inc
action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
depends "$(MAINBOARD)/auto.c option_table.h"
action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
end
makerule ./auto.inc
depends "./romcc ./auto.E"
@ -160,6 +163,31 @@ northbridge amd/amdk8 "mc0"
pci 1:0.1 on
pci 1:0.2 on
pci 1:1.0 off
superio winbond/w83627hf link 1
pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
pnp 2e.3 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
pnp 2e.6 off # CIR
pnp 2e.7 off # GAME_MIDI_GIPO1
pnp 2e.8 off # GPIO2
pnp 2e.9 off # GPIO3
pnp 2e.a off # ACPI
pnp 2e.b off # HW Monitor
end
end
end
@ -192,21 +220,9 @@ northbridge amd/amdk8 "mc3"
end
#northbridge amd/amdk8
#end
#southbridge amd/amd8111 "amd8111"
#end
#southbridge amd/amd8131 "amd8131"
#end
#mainboardinit archi386/smp/secondary.inc
#superio NSC/pc87360
# register "com1" = "{1}"
# register "lpt" = "{1}"
#end
dir /pc80
##dir /src/superio/winbond/w83627hf
#dir /bioscall
#dir /cpu/k8
cpu k8 "cpu0"
register "up" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
end

95
src/mainboard/tyan/s4880/auto.c
View File

@ -1,13 +1,16 @@
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <cpu/p6/apic.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/smp/lapic.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include "northbridge/amd/amdk8/early_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/k8/apic_timer.c"
@ -16,6 +19,25 @@
#include "northbridge/amd/amdk8/reset_test.c"
#include "debug.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static void hard_reset(void)
{
set_bios_reset();
/* enable cf9 */
pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
/* reset */
outb(0x0e, 0x0cf9);
}
static void soft_reset(void)
{
set_bios_reset();
pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
}
#define REV_B_RESET 0
@ -102,8 +124,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
/* include mainboard specific ht code */
#include "hypertransport.c"
//#include "northbridge/amd/amdk8/cpu_ldtstop.c"
//#include "southbridge/amd/amd8111/amd8111_ldtstop.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
@ -111,38 +131,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "resourcemap.c" /* tyan does not want the default */
static void enable_lapic(void)
{
msr_t msr;
msr = rdmsr(0x1b);
msr.hi &= 0xffffff00;
msr.lo &= 0x000007ff;
msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
wrmsr(0x1b, msr);
}
static void stop_this_cpu(void)
{
unsigned apicid;
apicid = apic_read(APIC_ID) >> 24;
/* Send an APIC INIT to myself */
apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
/* Wait for the ipi send to finish */
apic_wait_icr_idle();
/* Deassert the APIC INIT */
apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
/* Wait for the ipi send to finish */
apic_wait_icr_idle();
/* If I haven't halted spin forever */
for(;;) {
hlt();
}
}
#define FIRST_CPU 1
#define SECOND_CPU 1
@ -214,21 +202,26 @@ static void main(void)
#endif
};
int i;
if (cpu_init_detected()) {
asm("jmp __cpu_reset");
}
enable_lapic();
init_timer();
if (!boot_cpu() ) {
// notify_bsp_ap_is_stopped();
stop_this_cpu();
}
uart_init();
console_init();
setup_s4880_resource_map();
setup_coherent_ht_domain();
enumerate_ht_chain(0);
distinguish_cpu_resets(0);
int needs_reset;
enable_lapic();
init_timer();
if (cpu_init_detected()) {
asm("jmp __cpu_reset");
}
distinguish_cpu_resets();
if (!boot_cpu()) {
stop_this_cpu();
}
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
setup_s4880_resource_map();
needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
if (needs_reset) {
print_info("ht reset -");
soft_reset();
}
#if 0
dump_pci_devices();

26
src/mainboard/tyan/s4880/cmos.layout
View File

@ -29,6 +29,9 @@ entries
386 1 e 1 ECC_memory
388 4 r 0 reboot_bits
392 3 e 5 baud_rate
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
416 4 e 7 boot_first
@ -36,7 +39,14 @@ entries
424 4 e 7 boot_third
428 4 h 0 boot_index
432 8 h 0 boot_countdown
1008 16 h 0 check_sum
440 4 e 9 slow_cpu
444 1 e 1 nmi
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 reserved_memory
enumerations
@ -66,9 +76,21 @@ enumerations
7 9 Fallback_HDD
7 10 Fallback_Floppy
#7 3 ROM
8 0 200Mhz
8 1 166Mhz
8 2 133Mhz
8 3 100Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
checksums
checksum 392 1007 1008
checksum 392 983 984

68
src/mainboard/tyan/s4880/failover.c
View File

@ -3,36 +3,78 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include "arch/romcc_io.h"
#include <arch/romcc_io.h>
#include <arch/smp/lapic.h>
#include "pc80/mc146818rtc_early.c"
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
#include "cpu/p6/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#define HAVE_REGPARM_SUPPORT 0
#if HAVE_REGPARM_SUPPORT
static unsigned long main(unsigned long bist)
{
#else
static void main(void)
{
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain(0);
unsigned long bist = 0;
#endif
/* Make cerain my local apic is useable */
enable_lapic();
/* Setup the 8111 */
amd8111_enable_rom();
/* Is this a cpu reset? */
/* Is this a cpu only reset? */
if (cpu_init_detected()) {
if (last_boot_normal()) {
asm("jmp __normal_image");
goto normal_image;
} else {
asm("jmp __cpu_reset");
goto cpu_reset;
}
}
/* Is this a secondary cpu? */
else if (!boot_cpu() && last_boot_normal()) {
asm("jmp __normal_image");
if (!boot_cpu()) {
if (last_boot_normal()) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Setup the 8111 */
amd8111_enable_rom();
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
asm("jmp __normal_image");
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
asm("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
asm("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
fallback_image:
#if HAVE_REGPARM_SUPPORT
return bist;
#else
return;
#endif
}

12
src/southbridge/amd/amd8131/amd8131_bridge.c
View File

@ -24,15 +24,15 @@ static void pcix_init(device_t dev)
/* Set drive strength */
word = pci_read_config16(dev, 0xe0);
word = 0x0404;
word = 0x0808;
pci_write_config16(dev, 0xe0, word);
word = pci_read_config16(dev, 0xe4);
word = 0x0404;
word = 0x0808;
pci_write_config16(dev, 0xe4, word);
/* Set impedance */
word = pci_read_config16(dev, 0xe8);
word = 0x0404;
word = 0x0f0f;
pci_write_config16(dev, 0xe8, word);
/* Set discard unrequested prefetch data */
@ -105,6 +105,12 @@ static void ioapic_enable(device_t dev)
value &= ~((1 << 1) | (1 << 0));
}
pci_write_config32(dev, 0x44, value);
//BY LYH
value = pci_read_config32(dev, 0x4);
value |= 6;
pci_write_config32(dev, 0x4, value);
//BY LYH END
}
static struct device_operations ioapic_ops = {

26
src/southbridge/amd/amd8151/amd8151_agp3.c
View File

@ -11,12 +11,16 @@
static void agp3bridge_init(device_t dev)
{
uint32_t dword;
uint8_t byte;
byte = pci_read_config32(dev, 0x04);
byte |= 0x07;
pci_write_config8(dev, 0x04, byte);
byte = pci_read_config32(dev, 0xce);
byte |= 3<<2;
pci_write_config8(dev, 0xce, byte);
dword = pci_read_config8(dev, 0x04);
dword |= 0x07;
pci_write_config8(dev, 0x04, dword);
return;
}
@ -31,7 +35,7 @@ static struct device_operations agp3bridge_ops = {
static struct pci_driver agp3bridge_driver __pci_driver = {
.ops = &agp3bridge_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = 0x7455,
.device = 0x7455, // AGP Bridge
};
@ -41,19 +45,19 @@ static void agp3dev_enable(device_t dev)
// AGP enable
value = pci_read_config32(dev, 0xa8);
value |= (1<<8);
value |= (3<<8)|2; //AGP 8x
pci_write_config32(dev, 0xa8, value);
/*
// linkA 8bit-->16bit
value = pci_read_config32(dev, 0xc4);
value |= (11<<24);
value |= (0x11<<24);
pci_write_config32(dev, 0xc4, value);
// linkA 200-->600
value = pci_read_config32(dev, 0xcc);
value |= (4<<8);
pci_write_config32(dev, 0xcc, value);
*/
value = pci_read_config32(dev, 0x4);
value |= 6;
@ -72,6 +76,6 @@ static struct device_operations agp3dev_ops = {
static struct pci_driver agp3dev_driver __pci_driver = {
.ops = &agp3dev_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = 0x7454,
.device = 0x7454, //AGP Device
};

2
src/stream/rom_stream.c
View File

@ -17,7 +17,7 @@ int stream_init(void)
{
rom = rom_start;
printk_spew("%6d:%s() - rom_stream: 0x%08lx - 0x%08lx\n",
printk_debug("%6d:%s() - rom_stream: 0x%08lx - 0x%08lx\n",
__LINE__, __FUNCTION__,
(unsigned long)rom_start,
(unsigned long)rom_end);

11
targets/tyan/s2880/Config.lb
View File

@ -65,6 +65,7 @@ uses HAVE_HARD_RESET
#
#uses CONFIG_LSI_SCSI_FW_FIXUP
option HAVE_HARD_RESET=1
option HAVE_OPTION_TABLE=1
@ -170,7 +171,7 @@ option TTYS0_BAUD=115200
## Request this level of debugging output
option DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging
option MAXIMUM_CONSOLE_LOGLEVEL=9
option MAXIMUM_CONSOLE_LOGLEVEL=8
option DEBUG=1
@ -180,14 +181,14 @@ option DEBUG=1
option _RAMBASE=0x004000
##
## Use a 128K stack
## Use a 128K stack
##
option STACK_SIZE=0x4000
##
## Use a 256K heap
## Use a 256K heap + 64
##
option HEAP_SIZE=0x8000
option HEAP_SIZE=0xa000
#
###
@ -233,7 +234,7 @@ romimage "fallback"
option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
mainboard tyan/s2880
payload ../../tg3.zelf
payload ../../tg3--ide_disk.zelf
end
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"

10
targets/tyan/s2881/Config.lb
View File

@ -170,7 +170,7 @@ option TTYS0_BAUD=115200
## Request this level of debugging output
option DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging
option MAXIMUM_CONSOLE_LOGLEVEL=9
option MAXIMUM_CONSOLE_LOGLEVEL=8
option DEBUG=1
@ -180,14 +180,14 @@ option DEBUG=1
option _RAMBASE=0x004000
##
## Use a 128K stack
## Use a 128K stack
##
option STACK_SIZE=0x4000
##
## Use a 256K heap
## Use a 256K heap + 64
##
option HEAP_SIZE=0x8000
option HEAP_SIZE=0xa000
#
###
@ -233,7 +233,7 @@ romimage "fallback"
option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
mainboard tyan/s2881
payload ../../tg3.zelf
payload ../../tg3--ide_disk.zelf
end
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"

27
targets/tyan/s2882/Config.lb
View File

@ -44,6 +44,9 @@ uses CONFIG_CHIP_CONFIGURE
uses CONFIG_CONSOLE_SERIAL8250
uses TTYS0_BAUD
#SMDC Support
#uses CONFIG_CONSOLE_SERIAL8250_2
#uses TTYS1_BAUD
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses DEBUG
@ -76,7 +79,7 @@ option k7=1
option k8=1
option ROM_SIZE=524288
option HAVE_HARD_RESET=0
option HAVE_HARD_RESET=1
#option CONFIG_VGABIOS=1
#option CONFIG_REALMODE_IDT=1
@ -84,7 +87,6 @@ option HAVE_HARD_RESET=0
#option VGABIOS_START=0xfff8c000
#option SCSIFW_START=0xfff80000
option HAVE_FALLBACK_BOOT=1
# use the new chip configure code.
@ -153,6 +155,11 @@ option CONFIG_COMPRESS=1
option CONFIG_CONSOLE_SERIAL8250=1
option TTYS0_BAUD=115200
#SMDC support
#option CONFIG_CONSOLE_SERIAL8250_2=1
#option TTYS1_BAUD=19200
##
### Select the linuxBIOS loglevel
##
@ -169,7 +176,7 @@ option TTYS0_BAUD=115200
## Request this level of debugging output
option DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging
option MAXIMUM_CONSOLE_LOGLEVEL=9
option MAXIMUM_CONSOLE_LOGLEVEL=8
option DEBUG=1
@ -179,14 +186,14 @@ option DEBUG=1
option _RAMBASE=0x004000
##
## Use a 128K stack
## Use a 128K stack
##
option STACK_SIZE=0x4000
##
## Use a 256K heap
## Use a 256K heap + 128
##
option HEAP_SIZE=0x8000
option HEAP_SIZE=0xa000
#
###
@ -215,7 +222,9 @@ romimage "normal"
option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
mainboard tyan/s2882
payload ../../tg3--ide_disk.zelf
payload ../../tg3--ide_disk.zelf
# SMDC support
# payload ../../tg3--ide_disk_com1_2.zelf
end
romimage "fallback"
@ -232,7 +241,9 @@ romimage "fallback"
option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
mainboard tyan/s2882
payload ../../tg3.zelf
payload ../../tg3--ide_disk.zelf
#SMDC support
# payload ../../tg3--ide_disk_com1_2.zelf
end
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"

12
targets/tyan/s2885/Config.lb
View File

@ -90,7 +90,7 @@ option CONFIG_CHIP_CONFIGURE=1
#option CONFIG_LSI_SCSI_FW_FIXUP=1
option HAVE_HARD_RESET=0
option HAVE_HARD_RESET=1
###
### Build code to export a programmable irq routing table
@ -134,7 +134,8 @@ option MAINBOARD_VENDOR="Tyan"
### (linuxBIOS plus bootloader) will live in the boot rom chip.
###
#option FALLBACK_SIZE=524288
option FALLBACK_SIZE=98304
#option FALLBACK_SIZE=98304
option FALLBACK_SIZE=131072
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
option ROM_IMAGE_SIZE=65536
@ -168,7 +169,7 @@ option TTYS0_BAUD=115200
## Request this level of debugging output
option DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging
option MAXIMUM_CONSOLE_LOGLEVEL=9
option MAXIMUM_CONSOLE_LOGLEVEL=8
option DEBUG=1
@ -183,9 +184,9 @@ option _RAMBASE=0x004000
option STACK_SIZE=0x4000
##
## Use a 256K heap
## Use a 256K heap + 64
##
option HEAP_SIZE=0x8000
option HEAP_SIZE=0xa000
#
###
@ -232,6 +233,7 @@ romimage "fallback"
mainboard tyan/s2885
payload ../../tg3--ide_disk.zelf
# payload ../../filo.elf.d
end
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"

6
targets/tyan/s4880/Config.lb
View File

@ -136,7 +136,8 @@ option MAINBOARD_VENDOR="Tyan"
### (linuxBIOS plus bootloader) will live in the boot rom chip.
###
#option FALLBACK_SIZE=524288
option FALLBACK_SIZE=98304
#option FALLBACK_SIZE=98304
option FALLBACK_SIZE=131072
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
option ROM_IMAGE_SIZE=65536
@ -233,7 +234,8 @@ romimage "fallback"
option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
mainboard tyan/s4880
payload ../../tg3.zelf
# payload ../../tg3--ide_disk.zelf
payload ../../filo.elf.d
end
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"