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mb/google/hatch: Enable SD card support for hatch 

Enable support for SD card support for hatch
1. Enable PCI device for SD and also configure SD detect GPIO
2. Configure SD card related GPIOs in gpio.c

BUG=b:120914069
BRANCH=none
TEST=Verify GPIO configuration with schematics

Change-Id: I8ccaa28323b1e1fcc192e245347a96309227660b
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/30545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
Maulik V Vaghela 2018-12-31 12:12:36 +05:30 committed by Subrata Banik
parent ec576d1c97
commit e4fcc3ba2c
2 changed files with 24 additions and 1 deletions
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5
src/mainboard/google/hatch/variants/baseboard/devicetree.cb
View File

@ -80,6 +80,9 @@ chip soc/intel/cannonlake
# ClkReq-to-ClkSrc mapping for CLK SRC 1 # ClkReq-to-ClkSrc mapping for CLK SRC 1
register "PcieClkSrcClkReq[1]" = "1" register "PcieClkSrcClkReq[1]" = "1"
# GPIO for SD card detect
register "sdcard_cd_gpio" = "GPP_G5"
device cpu_cluster 0 on device cpu_cluster 0 on
device lapic 0 on end device lapic 0 on end
end end
@ -173,7 +176,7 @@ chip soc/intel/cannonlake
register "wake" = "GPE0_PME_B0" register "wake" = "GPE0_PME_B0"
device pci 14.3 on end # CNVi wifi device pci 14.3 on end # CNVi wifi
end end
device pci 14.5 off end # SDCard device pci 14.5 on end # SDCard
device pci 15.0 on device pci 15.0 on
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""ELAN0000"" register "hid" = ""ELAN0000""

20
src/mainboard/google/hatch/variants/baseboard/gpio.c
View File

@ -19,6 +19,10 @@
#include <commonlib/helpers.h> #include <commonlib/helpers.h>
static const struct pad_config gpio_table[] = { static const struct pad_config gpio_table[] = {
/* SD_1P8_SEL => NC */
PAD_NC(GPP_A16, DN_20K),
/* EN_PP3300_SD_DX */
PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
/* TRACKPAD_INT_ODL */ /* TRACKPAD_INT_ODL */
PAD_CFG_GPI_APIC(GPP_A21, NONE, PLTRST, LEVEL, INVERT), PAD_CFG_GPI_APIC(GPP_A21, NONE, PLTRST, LEVEL, INVERT),
/* SRCCLKREQ1 */ /* SRCCLKREQ1 */
@ -95,6 +99,22 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPP_F11, NONE, PLTRST), PAD_CFG_GPI(GPP_F11, NONE, PLTRST),
/* PCH_MEM_STRAP3 */ /* PCH_MEM_STRAP3 */
PAD_CFG_GPI(GPP_F22, NONE, PLTRST), PAD_CFG_GPI(GPP_F22, NONE, PLTRST),
/* SD_CMD */
PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
/* SD_DATA0 */
PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
/* SD_DATA1 */
PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
/* SD_DATA2 */
PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
/* SD_DATA3 */
PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
/* SD_CD# */
PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
/* SD_CLK */
PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
/* SD_WP => NC */
PAD_NC(GPP_G7, DN_20K),
}; };
const struct pad_config *__weak variant_gpio_table(size_t *num) const struct pad_config *__weak variant_gpio_table(size_t *num)