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amd/gardenia: Correct PCIe port settings 

Fix the OEM settings for two ports.  Fix and clarify comments to
reflect Rev. B of the board design.

Change-Id: I2812ea5945f67229872e78041c771606047bbbec
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20744
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Marshall Dawson 2017-07-18 15:37:36 -06:00 committed by Martin Roth
parent e5c8077c94
commit e4ff2b75fa
1 changed files with 6 additions and 4 deletions
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10
src/mainboard/amd/gardenia/OemCustomize.c
View File

@ -17,11 +17,13 @@
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
/* Port descriptor list for Gardenia Rev. B */
static const PCIe_PORT_DESCRIPTOR PortList[] = { static const PCIe_PORT_DESCRIPTOR PortList[] = {
/* Init port descriptor (PCIe port, Lanes 7:4, D2F1) for x4 slot */ /* Init port descriptor (PCIe port, Lanes 7:4, D2F1) for x4 slot */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 4, 7), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
2, 1, 2, 1,
HotplugDisabled, HotplugDisabled,
@ -32,14 +34,15 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
/* Initialize Port descriptor (PCIe port, Lanes 1:0, D2F2) for M.2 */ /* Initialize Port descriptor (PCIe port, Lanes 1:0, D2F2) for M.2 */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 0, 1), PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 1),
PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db, PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
2, 2, 2, 2,
HotplugDisabled, HotplugDisabled,
PcieGenMaxSupported, PcieGenMaxSupported,
PcieGenMaxSupported, PcieGenMaxSupported,
AspmL0sL1, 0x17, 0) AspmL0sL1, 0x17, 0)
}, },
/* Disable M.2 x1 on lane 1, D2F3 */
{ {
0, 0,
PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 1, 1), PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 1, 1),
@ -72,7 +75,6 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
PcieGenMaxSupported, PcieGenMaxSupported,
AspmL0sL1, 0x16, 0) AspmL0sL1, 0x16, 0)
}, },
/* Initialize Port descriptor (PCIe port, Lane 1, D2F3) for M.2 */
}; };
static const PCIe_DDI_DESCRIPTOR DdiList[] = { static const PCIe_DDI_DESCRIPTOR DdiList[] = {