soc/amd/common/block: Create new SPI code
Create a new SPI code that overrides flash operations and uses the SPI controller within the FCH to its fullest. Reference: Family 15h models 70h-7Fh BKDG revision 3.06 (public) BUG=b:136595978 TEST=Build and boot grunt using this code, with debug enabled. Check output. Change-Id: Id293fb9b2da84c4206c7a1341b64e83fc0b8d71d Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
This commit is contained in:
Richard Spiegel
Martin Roth
parent
524bcbb494
commit
e512bce189
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@ -0,0 +1,87 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Silverback Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _FCH_SPI_H_
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#define _FCH_SPI_H_
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#include <stdint.h>
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#include <stddef.h>
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#define GRANULARITY_TEST_4k 0x0000f000 /* bits 15-12 */
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#define WORD_TO_DWORD_UPPER(x) ((x << 16) & 0xffff0000)
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#define SPI_PAGE_WRITE 0x02
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#define SPI_WRITE_ENABLE 0x06
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#define IDCODE_CONT_LEN 0
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#define IDCODE_PART_LEN 5
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#define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN)
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/* SPI MMIO registers */
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#define SPI_CNTRL0 0x00
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#define SPI_ACCESS_MAC_ROM_EN BIT(22)
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#define SPI_RESTRICTED_CMD1 0x04
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#define SPI_RESTRICTED_CMD2 0x08
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#define SPI_CNTRL1 0x0c
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#define SPI_CMD_CODE 0x45
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#define SPI_CMD_TRIGGER 0x47
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/* Special SST write commands */
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#define CMD_SST_BP 0x02 /* Byte Program */
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#define CMD_SST_AAI_WP 0xad /* Auto Address Increment Word Program */
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#define SST_256 0x004b /* Only SST that programs 256 bytes at once */
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enum non_standard_spi {
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NON_STANDARD_SPI_NONE = 0,
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NON_STANDARD_SPI_SST,
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};
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struct spi_flash_table {
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const u8 shift;
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const u8 idcode;
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int (*probe)(const struct spi_slave *spi, u8 *idcode,
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struct spi_flash *flash);
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};
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struct spi_data {
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const char *name;
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u32 size;
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u32 sector_size;
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u32 page_size;
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u8 status_cmd;
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u8 erase_cmd;
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u8 write_cmd;
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u8 write_enable_cmd;
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u8 read_cmd;
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u8 read_cmd_len;
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enum non_standard_spi non_standard;
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};
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void fch_spi_init(void);
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void fch_spi_flash_ops_init(struct spi_flash *flash);
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int fch_spi_flash_cmd(const void *dout, size_t bytes_out, void *din, size_t bytes_in);
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int fch_spi_flash_cmd_write(const u8 *cmd, size_t cmd_len, const void *data, size_t data_len);
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int fch_spi_wait_cmd_ready(unsigned long timeout);
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int non_standard_sst_byte_write(u32 offset, const void *buf);
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int non_standard_sst_write_aai(u32 offset, size_t len, const void *buf, size_t start);
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const struct spi_flash_table *get_spi_flash_table(int *table_size);
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const struct spi_data *get_ctrl_spi_data(void);
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static inline int fch_spi_enable_write(void)
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{
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u8 cmd_enable = SPI_WRITE_ENABLE;
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return fch_spi_flash_cmd(&cmd_enable, 1, NULL, 0);
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}
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#endif /* _FCH_SPI_H_ */
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@ -90,6 +90,14 @@
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#define DECODE_IO_PORT_ENABLE0_H BIT(0)
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#define LPC_MEM_PORT1 0x4c
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#define ROM_PROTECT_RANGE0 0x50
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#define ROM_BASE_MASK 0xfffff000 /* bits 31-12 */
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#define ROM_RANGE_WP BIT(10)
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#define ROM_RANGE_RP BIT(9)
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#define RANGE_UNIT BIT(8)
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#define RANGE_ADDR_MASK 0x000000ff /* Range defined by bits 7-0 */
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#define ROM_PROTECT_RANGE_REG(n) (ROM_PROTECT_RANGE0 + (4 * n))
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#define MAX_ROM_PROTECT_RANGES 4
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#define LPC_MEM_PORT0 0x60
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/* Register 0x64 is 32-bit, composed by two 16-bit sub-registers.
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@ -0,0 +1,11 @@
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config SOC_AMD_COMMON_BLOCK_SPI
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bool
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default n
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help
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Select this option to add FCH SPI controller functions to the build.
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This overwrites the structure spi_flash_ops to use FCH SPI code
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instead of individual SPI specific code.
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config SOC_AMD_COMMON_BLOCK_SPI_DEBUG
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bool
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default n
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@ -0,0 +1,30 @@
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ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SPI),y)
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bootblock-y += fch_spi_ctrl.c
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bootblock-y += fch_spi_flash.c
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bootblock-y += fch_spi_special.c
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bootblock-y += fch_spi_table.c
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romstage-y += fch_spi_ctrl.c
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romstage-y += fch_spi_flash.c
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romstage-y += fch_spi_special.c
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romstage-y += fch_spi_table.c
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verstage-y += fch_spi_ctrl.c
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verstage-y += fch_spi_flash.c
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verstage-y += fch_spi_special.c
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verstage-y += fch_spi_table.c
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postcar-y += fch_spi_ctrl.c
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postcar-y += fch_spi_flash.c
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postcar-y += fch_spi_special.c
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postcar-y += fch_spi_table.c
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ramstage-y += fch_spi_ctrl.c
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ramstage-y += fch_spi_flash.c
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ramstage-y += fch_spi_special.c
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ramstage-y += fch_spi_table.c
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ifeq ($(CONFIG_SPI_FLASH_SMM),y)
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smm-y += fch_spi_ctrl.c
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smm-y += fch_spi_flash.c
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smm-y += fch_spi_special.c
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smm-y += fch_spi_table.c
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endif
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endif
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@ -0,0 +1,427 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Silverback Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <spi_flash.h>
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#include <soc/southbridge.h>
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#include <soc/pci_devs.h>
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#include <amdblocks/fch_spi.h>
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#include <amdblocks/lpc.h>
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#include <drivers/spi/spi_flash_internal.h>
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#include <device/pci_ops.h>
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#include <timer.h>
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#include <lib.h>
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static struct spi_data ctrl_spi_data;
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static uint32_t spibar;
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static inline uint8_t spi_read8(uint8_t reg)
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{
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return read8((void *)(spibar + reg));
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}
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static inline uint32_t spi_read32(uint8_t reg)
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{
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return read32((void *)(spibar + reg));
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}
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static inline void spi_write8(uint8_t reg, uint8_t val)
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{
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write8((void *)(spibar + reg), val);
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}
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static inline void spi_write32(uint8_t reg, uint32_t val)
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{
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write32((void *)(spibar + reg), val);
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}
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static void dump_state(const char *str, u8 phase)
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{
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u8 dump_size;
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u32 addr;
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if (!CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG))
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return;
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printk(BIOS_DEBUG, "SPI: %s\n", str);
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printk(BIOS_DEBUG, "Cntrl0: %x\n", spi_read32(SPI_CNTRL0));
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printk(BIOS_DEBUG, "Status: %x\n", spi_read32(SPI_STATUS));
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addr = spibar + SPI_FIFO;
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if (phase == 0) {
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dump_size = spi_read8(SPI_TX_BYTE_COUNT);
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printk(BIOS_DEBUG, "TxByteCount: %x\n", dump_size);
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printk(BIOS_DEBUG, "CmdCode: %x\n", spi_read8(SPI_CMD_CODE));
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} else {
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dump_size = spi_read8(SPI_RX_BYTE_COUNT);
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printk(BIOS_DEBUG, "RxByteCount: %x\n", dump_size);
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addr += spi_read8(SPI_TX_BYTE_COUNT);
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}
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if (dump_size > 0)
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hexdump((void *)addr, dump_size);
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}
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static int wait_for_ready(void)
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{
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const uint32_t timeout_ms = 500;
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struct stopwatch sw;
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stopwatch_init_msecs_expire(&sw, timeout_ms);
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do {
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if (!(spi_read32(SPI_STATUS) & SPI_BUSY))
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return 0;
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} while (!stopwatch_expired(&sw));
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return -1;
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}
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static int execute_command(void)
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{
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dump_state("Before execute", 0);
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spi_write8(SPI_CMD_TRIGGER, SPI_CMD_TRIGGER_EXECUTE);
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if (wait_for_ready())
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printk(BIOS_ERR,
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"FCH_SC Error: Timeout executing command\n");
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dump_state("Transaction finished", 1);
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return 0;
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}
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void spi_init(void)
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{
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spibar = lpc_get_spibase();
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printk(BIOS_DEBUG, "%s: Spibar at 0x%08x\n", __func__, spibar);
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}
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const struct spi_data *get_ctrl_spi_data(void)
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{
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return &ctrl_spi_data;
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}
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static int spi_ctrlr_xfer(const void *dout, size_t bytesout, void *din, size_t bytesin)
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{
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size_t count;
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uint8_t cmd;
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uint8_t *bufin = din;
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const uint8_t *bufout = dout;
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if (CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG))
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printk(BIOS_DEBUG, "%s(%zx, %zx)\n", __func__, bytesout,
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bytesin);
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/* First byte is cmd which cannot be sent through FIFO */
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cmd = bufout[0];
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bufout++;
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bytesout--;
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/*
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* Check if this is a write command attempting to transfer more bytes
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* than the controller can handle. Iterations for writes are not
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* supported here because each SPI write command needs to be preceded
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* and followed by other SPI commands.
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*/
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if (bytesout + bytesin > SPI_FIFO_DEPTH) {
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printk(BIOS_WARNING, "FCH_SC: Too much to transfer, code error!\n");
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return -1;
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}
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if (wait_for_ready())
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return -1;
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spi_write8(SPI_CMD_CODE, cmd);
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spi_write8(SPI_TX_BYTE_COUNT, bytesout);
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spi_write8(SPI_RX_BYTE_COUNT, bytesin);
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for (count = 0; count < bytesout; count++)
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spi_write8(SPI_FIFO + count, bufout[count]);
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if (execute_command())
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return -1;
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for (count = 0; count < bytesin; count++)
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bufin[count] = spi_read8(SPI_FIFO + count + bytesout);
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return 0;
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}
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static int amd_xfer_vectors(struct spi_op vectors[], size_t count)
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{
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int ret;
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void *din;
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size_t bytes_in;
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if (count < 1 || count > 2)
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return -1;
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/* SPI flash commands always have a command first... */
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if (!vectors[0].dout || !vectors[0].bytesout)
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return -1;
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/* And not read any data during the command. */
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if (vectors[0].din || vectors[0].bytesin)
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return -1;
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if (count == 2) {
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/* If response bytes requested ensure the buffer is valid. */
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if (vectors[1].bytesin && !vectors[1].din)
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return -1;
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/* No sends can accompany a receive. */
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if (vectors[1].dout || vectors[1].bytesout)
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return -1;
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din = vectors[1].din;
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bytes_in = vectors[1].bytesin;
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} else {
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din = NULL;
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bytes_in = 0;
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}
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ret = spi_ctrlr_xfer(vectors[0].dout, vectors[0].bytesout, din, bytes_in);
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if (ret) {
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vectors[0].status = SPI_OP_FAILURE;
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if (count == 2)
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vectors[1].status = SPI_OP_FAILURE;
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} else {
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vectors[0].status = SPI_OP_SUCCESS;
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if (count == 2)
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vectors[1].status = SPI_OP_SUCCESS;
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}
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return ret;
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}
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int fch_spi_flash_cmd(const void *dout, size_t bytes_out, void *din, size_t bytes_in)
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{
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/*
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* SPI flash requires command-response kind of behavior. Thus, two
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* separate SPI vectors are required -- first to transmit dout and other
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* to receive in din.
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*/
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struct spi_op vectors[] = {
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[0] = { .dout = dout, .bytesout = bytes_out,
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.din = NULL, .bytesin = 0, },
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[1] = { .dout = NULL, .bytesout = 0,
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.din = din, .bytesin = bytes_in },
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};
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size_t count = ARRAY_SIZE(vectors);
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if (!bytes_in)
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count = 1;
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return amd_xfer_vectors(vectors, count);
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}
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static void set_ctrl_spi_data(struct spi_flash *flash)
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{
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u8 cmd = SPI_PAGE_WRITE;
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ctrl_spi_data.name = flash->name;
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ctrl_spi_data.size = flash->size;
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ctrl_spi_data.sector_size = flash->sector_size;
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ctrl_spi_data.status_cmd = flash->status_cmd;
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ctrl_spi_data.erase_cmd = flash->erase_cmd;
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ctrl_spi_data.write_enable_cmd = SPI_WRITE_ENABLE;
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if (flash->vendor == VENDOR_ID_SST) {
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ctrl_spi_data.non_standard = NON_STANDARD_SPI_SST;
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if ((flash->model & 0x00ff) == SST_256)
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ctrl_spi_data.page_size = 256;
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else {
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ctrl_spi_data.page_size = 2;
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cmd = CMD_SST_AAI_WP;
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}
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} else {
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ctrl_spi_data.page_size = flash->page_size;
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ctrl_spi_data.non_standard = NON_STANDARD_SPI_NONE;
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}
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ctrl_spi_data.write_cmd = cmd;
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if (CONFIG(SPI_FLASH_NO_FAST_READ)) {
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ctrl_spi_data.read_cmd_len = 4;
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ctrl_spi_data.read_cmd = CMD_READ_ARRAY_SLOW;
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} else {
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ctrl_spi_data.read_cmd_len = 5;
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ctrl_spi_data.read_cmd = CMD_READ_ARRAY_FAST;
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}
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}
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static int fch_spi_flash_probe(const struct spi_slave *spi, struct spi_flash *flash)
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{
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int ret, i, shift, table_size;
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u8 idcode[IDCODE_LEN], *idp, cmd = CMD_READ_ID;
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const struct spi_flash_table *flash_ptr = get_spi_flash_table(&table_size);
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/* Read the ID codes */
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ret = fch_spi_flash_cmd(&cmd, 1, idcode, sizeof(idcode));
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if (ret)
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return -1;
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if (CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG)) {
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printk(BIOS_SPEW, "SF: Got idcode: ");
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for (i = 0; i < sizeof(idcode); i++)
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printk(BIOS_SPEW, "%02x ", idcode[i]);
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printk(BIOS_SPEW, "\n");
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}
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/* count the number of continuation bytes */
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for (shift = 0, idp = idcode; shift < IDCODE_CONT_LEN && *idp == 0x7f;
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++shift, ++idp)
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continue;
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printk(BIOS_INFO, "Manufacturer: %02x\n", *idp);
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/* search the table for matches in shift and id */
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for (i = 0; i < table_size; ++i) {
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if (flash_ptr->shift == shift && flash_ptr->idcode == *idp) {
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/* we have a match, call probe */
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if (flash_ptr->probe(spi, idp, flash) == 0) {
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flash->vendor = idp[0];
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flash->model = (idp[1] << 8) | idp[2];
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set_ctrl_spi_data(flash);
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fch_spi_flash_ops_init(flash);
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return 0;
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}
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}
|
||||
flash_ptr++;
|
||||
}
|
||||
|
||||
/* No match, return error. */
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int protect_a_range(u32 value)
|
||||
{
|
||||
u32 reg32;
|
||||
u8 n;
|
||||
|
||||
/* find a free protection register */
|
||||
for (n = 0; n < MAX_ROM_PROTECT_RANGES; n++) {
|
||||
reg32 = pci_read_config32(SOC_LPC_DEV, ROM_PROTECT_RANGE_REG(n));
|
||||
if (!reg32)
|
||||
break;
|
||||
}
|
||||
if (n == MAX_ROM_PROTECT_RANGES)
|
||||
return -1; /* no free range */
|
||||
|
||||
pci_write_config32(SOC_LPC_DEV, ROM_PROTECT_RANGE_REG(n), value);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Protect range of SPI flash defined by region using the SPI flash controller.
|
||||
*
|
||||
* Note: Up to 4 ranges can be protected, though if a particular region requires more than one
|
||||
* range, total number of regions decreases accordingly. Each range can be programmed to 4KiB or
|
||||
* 64KiB granularity.
|
||||
*
|
||||
* Warning: If more than 1 region needs protection, and they need mixed protections (read/write)
|
||||
* than start with the region that requires the most protection. After the restricted commands
|
||||
* have been written, they can't be changed (write once). So if first region is write protection
|
||||
* and second region is read protection, it's best to define first region as read and write
|
||||
* protection.
|
||||
*/
|
||||
static int fch_spi_flash_protect(const struct spi_flash *flash, const struct region *region,
|
||||
const enum ctrlr_prot_type type)
|
||||
{
|
||||
int ret;
|
||||
u32 reg32, rom_base, range_base;
|
||||
size_t addr, len, gran_value, total_ranges, range;
|
||||
bool granularity_64k = true; /* assume 64k granularity */
|
||||
|
||||
addr = region->offset;
|
||||
len = region->size;
|
||||
|
||||
reg32 = pci_read_config32(SOC_LPC_DEV, ROM_ADDRESS_RANGE2_START);
|
||||
rom_base = WORD_TO_DWORD_UPPER(reg32);
|
||||
if (addr < rom_base)
|
||||
return -1;
|
||||
range_base = addr % rom_base;
|
||||
|
||||
/* Define granularity to be used */
|
||||
if (GRANULARITY_TEST_4k & range_base)
|
||||
granularity_64k = false; /* use 4K granularity */
|
||||
if (GRANULARITY_TEST_4k & len)
|
||||
granularity_64k = false; /* use 4K granularity */
|
||||
|
||||
/* Define the first range and total number of ranges required */
|
||||
if (granularity_64k) {
|
||||
gran_value = 0x00010000; /* 64 KiB */
|
||||
range_base = range_base >> 16;
|
||||
} else {
|
||||
gran_value = 0x00001000; /* 4 KiB */
|
||||
range_base = range_base >> 12;
|
||||
}
|
||||
total_ranges = len / gran_value;
|
||||
range_base &= RANGE_ADDR_MASK;
|
||||
|
||||
/* Create reg32 to be written into a range register and program required ranges */
|
||||
reg32 = rom_base & ROM_BASE_MASK;
|
||||
reg32 |= range_base;
|
||||
if (granularity_64k)
|
||||
reg32 |= RANGE_UNIT;
|
||||
if (type & WRITE_PROTECT)
|
||||
reg32 |= ROM_RANGE_WP;
|
||||
if (type & READ_PROTECT)
|
||||
reg32 |= ROM_RANGE_RP;
|
||||
|
||||
for (range = 0; range < total_ranges; range++) {
|
||||
ret = protect_a_range(reg32);
|
||||
if (ret)
|
||||
return ret;
|
||||
/*
|
||||
* Next range (lower 8 bits). Range points to the start address of a region.
|
||||
* The range value must be multiplied by the granularity (which is also the
|
||||
* size of the region) to get the actual offset from the SPI start address.
|
||||
*/
|
||||
reg32++;
|
||||
}
|
||||
|
||||
/* define commands to be blocked if in range */
|
||||
reg32 = 0;
|
||||
if (type & WRITE_PROTECT) {
|
||||
reg32 |= (ctrl_spi_data.write_enable_cmd << 24);
|
||||
reg32 |= (ctrl_spi_data.write_cmd << 16);
|
||||
reg32 |= (ctrl_spi_data.erase_cmd << 8);
|
||||
}
|
||||
if (type & READ_PROTECT)
|
||||
reg32 |= ctrl_spi_data.read_cmd;
|
||||
|
||||
/* Final steps to protect region */
|
||||
pci_write_config32(SOC_LPC_DEV, SPI_RESTRICTED_CMD1, reg32);
|
||||
reg32 = spi_read32(SPI_CNTRL0);
|
||||
reg32 &= ~SPI_ACCESS_MAC_ROM_EN;
|
||||
spi_write32(SPI_CNTRL0, reg32);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct spi_ctrlr fch_spi_flash_ctrlr = {
|
||||
.max_xfer_size = SPI_FIFO_DEPTH,
|
||||
.flash_probe = fch_spi_flash_probe,
|
||||
.flash_protect = fch_spi_flash_protect,
|
||||
};
|
||||
|
||||
const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
|
||||
{
|
||||
.ctrlr = &fch_spi_flash_ctrlr,
|
||||
.bus_start = 0,
|
||||
.bus_end = 0,
|
||||
},
|
||||
};
|
||||
|
||||
const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);
|
||||
|
|
@ -0,0 +1,246 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 Silverback Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <spi_flash.h>
|
||||
#include <soc/southbridge.h>
|
||||
#include <amdblocks/fch_spi.h>
|
||||
#include <drivers/spi/spi_flash_internal.h>
|
||||
#include <timer.h>
|
||||
#include <string.h>
|
||||
|
||||
static void spi_flash_addr(u32 addr, u8 *cmd)
|
||||
{
|
||||
/* cmd[0] is actual command */
|
||||
cmd[1] = addr >> 16;
|
||||
cmd[2] = addr >> 8;
|
||||
cmd[3] = addr >> 0;
|
||||
}
|
||||
|
||||
static int crop_chunk(unsigned int cmd_len, unsigned int buf_len)
|
||||
{
|
||||
return min((SPI_FIFO_DEPTH - (cmd_len - 1)), buf_len);
|
||||
}
|
||||
|
||||
int fch_spi_flash_cmd_write(const u8 *cmd, size_t cmd_len, const void *data, size_t data_len)
|
||||
{
|
||||
int ret;
|
||||
u8 buff[SPI_FIFO_DEPTH + 1];
|
||||
|
||||
if ((cmd_len + data_len) > SPI_FIFO_DEPTH)
|
||||
return -1;
|
||||
memcpy(buff, cmd, cmd_len);
|
||||
memcpy(buff + cmd_len, data, data_len);
|
||||
|
||||
ret = fch_spi_flash_cmd(buff, cmd_len + data_len, NULL, 0);
|
||||
if (ret) {
|
||||
printk(BIOS_WARNING, "FCH_SF: Failed to send write command (%zu bytes): %d\n",
|
||||
data_len, ret);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int fch_spi_flash_status(const struct spi_flash *flash, uint8_t *reg)
|
||||
{
|
||||
int ret;
|
||||
u8 status, cmd = CMD_READ_STATUS;
|
||||
|
||||
ret = fch_spi_flash_cmd(&cmd, 1, &status, 1);
|
||||
if (!ret)
|
||||
*reg = status;
|
||||
return ret;
|
||||
}
|
||||
|
||||
int fch_spi_wait_cmd_ready(unsigned long timeout)
|
||||
{
|
||||
struct mono_time current, end;
|
||||
int ret;
|
||||
u8 status;
|
||||
|
||||
timer_monotonic_get(¤t);
|
||||
end = current;
|
||||
mono_time_add_msecs(&end, timeout);
|
||||
|
||||
do {
|
||||
ret = fch_spi_flash_status(NULL, &status);
|
||||
if (ret)
|
||||
return -1;
|
||||
if ((status & STATUS_WIP) == 0)
|
||||
return 0;
|
||||
timer_monotonic_get(¤t);
|
||||
} while (!mono_time_after(¤t, &end));
|
||||
|
||||
printk(BIOS_DEBUG, "FCH_SF: timeout at %ld msec\n", timeout);
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int fch_spi_flash_erase(const struct spi_flash *flash, uint32_t offset, size_t len)
|
||||
{
|
||||
u32 start, end, erase_size;
|
||||
const struct spi_data *spi_data_ptr = get_ctrl_spi_data();
|
||||
int ret = -1;
|
||||
u8 cmd[4];
|
||||
|
||||
erase_size = spi_data_ptr->sector_size;
|
||||
if (offset % erase_size || len % erase_size) {
|
||||
printk(BIOS_WARNING, "%s: Erase offset/length not multiple of erase size\n",
|
||||
spi_data_ptr->name);
|
||||
return -1;
|
||||
}
|
||||
if (len == 0) {
|
||||
printk(BIOS_WARNING, "%s: Erase length cannot be 0\n", spi_data_ptr->name);
|
||||
return -1;
|
||||
}
|
||||
|
||||
cmd[0] = spi_data_ptr->erase_cmd;
|
||||
start = offset;
|
||||
end = start + len;
|
||||
|
||||
while (offset < end) {
|
||||
spi_flash_addr(offset, cmd);
|
||||
offset += erase_size;
|
||||
|
||||
#if CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG)
|
||||
printk(BIOS_DEBUG, "FCH_SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
|
||||
cmd[2], cmd[3], offset);
|
||||
#endif
|
||||
ret = fch_spi_enable_write();
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
ret = fch_spi_flash_cmd_write(cmd, sizeof(cmd), NULL, 0);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
ret = fch_spi_wait_cmd_ready(SPI_FLASH_PAGE_ERASE_TIMEOUT_MS);
|
||||
if (ret)
|
||||
goto out;
|
||||
}
|
||||
|
||||
printk(BIOS_DEBUG, "%s: Successfully erased %zu bytes @ %#x\n", spi_data_ptr->name, len,
|
||||
start);
|
||||
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int fch_spi_flash_read(const struct spi_flash *flash, uint32_t offset, size_t len,
|
||||
void *buf)
|
||||
{
|
||||
const struct spi_data *spi_data_ptr = get_ctrl_spi_data();
|
||||
uint8_t *data = buf;
|
||||
int ret;
|
||||
size_t xfer_len;
|
||||
u8 cmd[5];
|
||||
|
||||
cmd[0] = spi_data_ptr->read_cmd;
|
||||
cmd[4] = 0;
|
||||
while (len) {
|
||||
xfer_len = crop_chunk(spi_data_ptr->read_cmd_len, len);
|
||||
spi_flash_addr(offset, cmd);
|
||||
ret = fch_spi_flash_cmd(cmd, spi_data_ptr->read_cmd_len, data, xfer_len);
|
||||
if (ret) {
|
||||
printk(BIOS_WARNING,
|
||||
"FCH_SF: Failed to send read command %#.2x(%#x, %#zx): %d\n",
|
||||
cmd[0], offset, xfer_len, ret);
|
||||
return ret;
|
||||
}
|
||||
offset += xfer_len;
|
||||
data += xfer_len;
|
||||
len -= xfer_len;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fch_spi_flash_write(const struct spi_flash *flash, uint32_t offset, size_t len,
|
||||
const void *buf)
|
||||
{
|
||||
unsigned long byte_addr;
|
||||
unsigned long page_size;
|
||||
const struct spi_data *spi_data_ptr = get_ctrl_spi_data();
|
||||
size_t chunk_len;
|
||||
size_t actual, start = 0;
|
||||
int ret = 0;
|
||||
u8 cmd[4];
|
||||
|
||||
page_size = spi_data_ptr->page_size;
|
||||
if (spi_data_ptr->non_standard == NON_STANDARD_SPI_SST) {
|
||||
if (offset % 2) {
|
||||
ret = non_standard_sst_byte_write(offset, buf);
|
||||
len--;
|
||||
start++;
|
||||
offset++;
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
if (page_size == 2)
|
||||
return non_standard_sst_write_aai(offset, len, buf, start);
|
||||
}
|
||||
|
||||
for (actual = start; actual < len; actual += chunk_len) {
|
||||
byte_addr = offset % page_size;
|
||||
chunk_len = min(len - actual, page_size - byte_addr);
|
||||
chunk_len = crop_chunk(sizeof(cmd), chunk_len);
|
||||
|
||||
cmd[0] = spi_data_ptr->write_cmd;
|
||||
cmd[1] = (offset >> 16) & 0xff;
|
||||
cmd[2] = (offset >> 8) & 0xff;
|
||||
cmd[3] = offset & 0xff;
|
||||
#if CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG)
|
||||
printk(BIOS_DEBUG, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu"
|
||||
"\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
|
||||
#endif
|
||||
|
||||
ret = fch_spi_enable_write();
|
||||
if (ret < 0) {
|
||||
printk(BIOS_WARNING, "%s: Enabling Write failed\n", spi_data_ptr->name);
|
||||
goto out;
|
||||
}
|
||||
|
||||
ret = fch_spi_flash_cmd_write(cmd, sizeof(cmd), buf + actual, chunk_len);
|
||||
if (ret < 0) {
|
||||
printk(BIOS_WARNING, "%s: Page Program failed\n", spi_data_ptr->name);
|
||||
goto out;
|
||||
}
|
||||
|
||||
ret = fch_spi_wait_cmd_ready(SPI_FLASH_PROG_TIMEOUT_MS);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
offset += chunk_len;
|
||||
}
|
||||
|
||||
#if CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG)
|
||||
printk(BIOS_DEBUG, "%s: Successfully programmed %zu bytes @ 0x%lx\n",
|
||||
spi_data_ptr->name, len, (unsigned long)(offset - len));
|
||||
#endif
|
||||
ret = 0;
|
||||
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct spi_flash_ops fch_spi_flash_ops = {
|
||||
.read = fch_spi_flash_read,
|
||||
.write = fch_spi_flash_write,
|
||||
.erase = fch_spi_flash_erase,
|
||||
.status = fch_spi_flash_status,
|
||||
};
|
||||
|
||||
void fch_spi_flash_ops_init(struct spi_flash *flash)
|
||||
{
|
||||
flash->ops = &fch_spi_flash_ops;
|
||||
}
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 Silverback Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <spi-generic.h>
|
||||
#include <amdblocks/fch_spi.h>
|
||||
#include <string.h>
|
||||
|
||||
int non_standard_sst_byte_write(u32 offset, const void *buf)
|
||||
{
|
||||
int ret;
|
||||
u8 cmd[4] = {
|
||||
CMD_SST_BP,
|
||||
offset >> 16,
|
||||
offset >> 8,
|
||||
offset,
|
||||
};
|
||||
|
||||
ret = fch_spi_enable_write();
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = fch_spi_flash_cmd_write(cmd, sizeof(cmd), buf, 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return fch_spi_wait_cmd_ready(SPI_FLASH_PROG_TIMEOUT_MS);
|
||||
}
|
||||
|
||||
int non_standard_sst_write_aai(u32 offset, size_t len, const void *buf, size_t start)
|
||||
{
|
||||
size_t actual, cmd_len;
|
||||
int ret = 0;
|
||||
u8 cmd[4];
|
||||
|
||||
ret = fch_spi_enable_write();
|
||||
if (ret)
|
||||
goto done;
|
||||
|
||||
cmd_len = 4;
|
||||
cmd[0] = CMD_SST_AAI_WP;
|
||||
cmd[1] = offset >> 16;
|
||||
cmd[2] = offset >> 8;
|
||||
cmd[3] = offset;
|
||||
|
||||
for (actual = start; actual < len - 1; actual += 2) {
|
||||
#if CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG)
|
||||
printk(BIOS_DEBUG, "PP: 0x%p => cmd = { 0x%02x 0x%06lx }"
|
||||
" chunk_len = 2\n",
|
||||
buf + actual, cmd[0], (offset + actual));
|
||||
#endif
|
||||
|
||||
ret = fch_spi_enable_write();
|
||||
if (ret < 0) {
|
||||
printk(BIOS_WARNING, "SF: Enabling Write failed\n");
|
||||
break;
|
||||
}
|
||||
|
||||
ret = fch_spi_flash_cmd_write(cmd, cmd_len, buf + actual, 2);
|
||||
if (ret < 0) {
|
||||
printk(BIOS_WARNING, "SF: SST word Program failed\n");
|
||||
break;
|
||||
}
|
||||
|
||||
ret = fch_spi_wait_cmd_ready(SPI_FLASH_PROG_TIMEOUT_MS);
|
||||
if (ret)
|
||||
break;
|
||||
|
||||
offset += 2;
|
||||
cmd_len = 1;
|
||||
}
|
||||
/* If there is a single trailing byte, write it out */
|
||||
if (!ret && actual != len)
|
||||
ret = non_standard_sst_byte_write(offset, buf + actual);
|
||||
done:
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 Silverback Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <spi_flash.h>
|
||||
#include <amdblocks/fch_spi.h>
|
||||
#include <drivers/spi/spi_flash_internal.h>
|
||||
|
||||
/*
|
||||
* The following table holds all device probe functions
|
||||
*
|
||||
* shift: number of continuation bytes before the ID
|
||||
* idcode: the expected IDCODE or 0xff for non JEDEC devices
|
||||
* probe: the function to call
|
||||
*
|
||||
* Non JEDEC devices should be ordered in the table such that
|
||||
* the probe functions with best detection algorithms come first.
|
||||
*
|
||||
* Several matching entries are permitted, they will be tried
|
||||
* in sequence until a probe function returns non NULL.
|
||||
*
|
||||
* IDCODE_CONT_LEN may be redefined if a device needs to declare a
|
||||
* larger "shift" value. IDCODE_PART_LEN generally shouldn't be
|
||||
* changed. This is the max number of bytes probe functions may
|
||||
* examine when looking up part-specific identification info.
|
||||
*
|
||||
* Probe functions will be given the idcode buffer starting at their
|
||||
* manu id byte (the "idcode" in the table below). In other words,
|
||||
* all of the continuation bytes will be skipped (the "shift" below).
|
||||
*/
|
||||
|
||||
const struct spi_flash_table flashes[] = {
|
||||
/* Keep it sorted by define name */
|
||||
#if CONFIG(SPI_FLASH_ADESTO)
|
||||
{ 0, VENDOR_ID_ADESTO, spi_flash_probe_adesto, },
|
||||
#endif
|
||||
#if CONFIG(SPI_FLASH_AMIC)
|
||||
{ 0, VENDOR_ID_AMIC, spi_flash_probe_amic, },
|
||||
#endif
|
||||
#if CONFIG(SPI_FLASH_ATMEL)
|
||||
{ 0, VENDOR_ID_ATMEL, spi_flash_probe_atmel, },
|
||||
#endif
|
||||
#if CONFIG(SPI_FLASH_EON)
|
||||
{ 0, VENDOR_ID_EON, spi_flash_probe_eon, },
|
||||
#endif
|
||||
#if CONFIG(SPI_FLASH_GIGADEVICE)
|
||||
{ 0, VENDOR_ID_GIGADEVICE, spi_flash_probe_gigadevice, },
|
||||
#endif
|
||||
#if CONFIG(SPI_FLASH_MACRONIX)
|
||||
{ 0, VENDOR_ID_MACRONIX, spi_flash_probe_macronix, },
|
||||
#endif
|
||||
#if CONFIG(SPI_FLASH_SPANSION)
|
||||
{ 0, VENDOR_ID_SPANSION, spi_flash_probe_spansion, },
|
||||
#endif
|
||||
#if CONFIG(SPI_FLASH_SST)
|
||||
{ 0, VENDOR_ID_SST, spi_flash_probe_sst, },
|
||||
#endif
|
||||
#if CONFIG(SPI_FLASH_STMICRO)
|
||||
{ 0, VENDOR_ID_STMICRO, spi_flash_probe_stmicro, },
|
||||
{ 0, VENDOR_ID_STMICRO_FF, spi_flash_probe_stmicro, },
|
||||
#endif
|
||||
#if CONFIG(SPI_FLASH_WINBOND)
|
||||
{ 0, VENDOR_ID_WINBOND, spi_flash_probe_winbond, },
|
||||
#endif
|
||||
/* Keep it sorted by best detection */
|
||||
};
|
||||
|
||||
const struct spi_flash_table *get_spi_flash_table(int *table_size)
|
||||
{
|
||||
*table_size = (int)ARRAY_SIZE(flashes);
|
||||
return &flashes[0];
|
||||
}
|
||||
Loading…
Reference in New Issue