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AGESA f14: Fix memory clock register decoding 

Bottom five LSBs are used to store the running frequency
of memory clock.

Change-Id: I2dfcf1950883836499ea2ca95f9eb72ccdfb979c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19042
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Kyösti Mälkki 2017-03-27 19:02:55 +03:00
parent e223c3aee9
commit e522258907
1 changed files with 2 additions and 1 deletions
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3
src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c
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@ -528,7 +528,8 @@ MemMSetCSRNb (
IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: DIMM config changed\n");
RetVal = FALSE;
}
if (((Value & 0x4000) == 0) && (NBPtr->GetMemClkFreqId (NBPtr, NBPtr->DCTPtr->Timings.TargetSpeed) != ((Value & 7) + 1))) {
if (((Value & 0x4000) == 0) && (NBPtr->GetMemClkFreqId (NBPtr,
NBPtr->DCTPtr->Timings.TargetSpeed) != (Value & 0x1f))) {
IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: MemClk has changed\n");
RetVal = FALSE;
}