fix up the links for the ultra 40 -- i/o on ht 1 on each cpu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2368 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -201,7 +201,8 @@ chip northbridge/amd/amdk8/root_complex
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end
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device pci_domain 0 on
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chip northbridge/amd/amdk8 #mc0
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device pci 18.0 on
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device pci 18.0 on end # link 0
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device pci 18.0 on # link1
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# devices on link 0, link 0 == LDT 0
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chip southbridge/nvidia/ck804
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device pci 0.0 on end # HT
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@ -318,30 +319,16 @@ chip northbridge/amd/amdk8/root_complex
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register "mac_eeprom_addr" = "0x51"
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end
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end # device pci 18.0
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device pci 18.0 on end # Link 1
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device pci 18.0 on
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# devices on link 2, link 2 == LDT 2
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chip southbridge/amd/amd8131
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# the on/off keyword is mandatory
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device pci 0.0 on end
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device pci 0.1 on end
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device pci 1.0 on
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chip drivers/pci/onboard
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device pci 6.0 on end # lsi scsi
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device pci 6.1 on end
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end
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end
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device pci 1.1 on end
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end
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end # device pci 18.0
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device pci 18.0 on end # link 2
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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end # mc0
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chip northbridge/amd/amdk8
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device pci 19.0 on # northbridge
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# devices on link 0, link 0 == LDT 0
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device pci 19.0 on end # link 0
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device pci 19.0 on
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# devices on link 1, link 1 == LDT 1
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chip southbridge/nvidia/ck804
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device pci 0.0 on end # HT
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device pci 1.0 on end # LPC
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@ -365,7 +352,6 @@ chip northbridge/amd/amdk8/root_complex
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end
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end # device pci 19.0
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device pci 19.0 on end
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device pci 19.0 on end
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device pci 19.1 on end
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device pci 19.2 on end
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@ -373,14 +359,4 @@ chip northbridge/amd/amdk8/root_complex
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end
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end # PCI domain
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# chip drivers/generic/debug
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# device pnp 0.0 off end # chip name
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# device pnp 0.1 off end # pci_regs_all
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# device pnp 0.2 off end # mem
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# device pnp 0.3 off end # cpuid
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# device pnp 0.4 on end # smbus_regs_all
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# device pnp 0.5 off end # dual core msr
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# device pnp 0.6 off end # cache size
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# device pnp 0.7 off end # tsc
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# end
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end #root_complex
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