soc/intel/p2sb: Drop unnecessary P2SB_GET_DEV
PCH_DEV_P2SB already covers both __SIMPLE_DEVICE__ cases. The values are only used for PCI-config access functions, which also check for NULL when necessary. The PCI_DEV_INVALID case can't occur by definition, and if we wanted to check, we could do so at compile time using _Static_assert(). Change-Id: I400fc20133809aaa0fd0519531a62ec9b8812ef1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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@ -29,40 +29,14 @@
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#define HIDE_BIT (1 << 0)
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#if defined(__SIMPLE_DEVICE__)
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static pci_devfn_t p2sb_get_device(void)
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{
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int devfn = PCH_DEVFN_P2SB;
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pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn));
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if (dev == PCI_DEV_INVALID)
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die_with_post_code(POST_HW_INIT_FAILURE,
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"PCH_DEV_P2SB not found!\n");
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return dev;
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}
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#else
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static struct device *p2sb_get_device(void)
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{
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struct device *dev = PCH_DEV_P2SB;
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if (!dev)
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die_with_post_code(POST_HW_INIT_FAILURE,
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"PCH_DEV_P2SB not found!\n");
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return dev;
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}
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#endif
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#define P2SB_GET_DEV p2sb_get_device()
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void p2sb_enable_bar(void)
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{
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/* Enable PCR Base address in PCH */
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pci_write_config32(P2SB_GET_DEV, PCI_BASE_ADDRESS_0, P2SB_BAR);
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pci_write_config32(P2SB_GET_DEV, PCI_BASE_ADDRESS_1, 0);
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pci_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, P2SB_BAR);
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pci_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_1, 0);
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/* Enable P2SB MSE */
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pci_write_config8(P2SB_GET_DEV, PCI_COMMAND,
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pci_write_config8(PCH_DEV_P2SB, PCI_COMMAND,
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PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
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}
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@ -79,7 +53,7 @@ void p2sb_configure_hpet(void)
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* the High Performance Timer memory address range
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* selected by bits 1:0
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*/
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pci_write_config8(P2SB_GET_DEV, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT);
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pci_write_config8(PCH_DEV_P2SB, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT);
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}
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static void p2sb_set_hide_bit(int hide)
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@ -88,18 +62,18 @@ static void p2sb_set_hide_bit(int hide)
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const uint8_t mask = HIDE_BIT;
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uint8_t val;
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val = pci_read_config8(P2SB_GET_DEV, reg);
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val = pci_read_config8(PCH_DEV_P2SB, reg);
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val &= ~mask;
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if (hide)
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val |= mask;
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pci_write_config8(P2SB_GET_DEV, reg, val);
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pci_write_config8(PCH_DEV_P2SB, reg, val);
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}
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void p2sb_unhide(void)
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{
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p2sb_set_hide_bit(0);
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if (pci_read_config16(P2SB_GET_DEV, PCI_VENDOR_ID) !=
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if (pci_read_config16(PCH_DEV_P2SB, PCI_VENDOR_ID) !=
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PCI_VENDOR_ID_INTEL)
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die_with_post_code(POST_HW_INIT_FAILURE,
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"Unable to unhide PCH_DEV_P2SB device !\n");
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@ -109,7 +83,7 @@ void p2sb_hide(void)
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{
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p2sb_set_hide_bit(1);
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if (pci_read_config16(P2SB_GET_DEV, PCI_VENDOR_ID) !=
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if (pci_read_config16(PCH_DEV_P2SB, PCI_VENDOR_ID) !=
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0xFFFF)
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die_with_post_code(POST_HW_INIT_FAILURE,
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"Unable to hide PCH_DEV_P2SB device !\n");
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@ -119,8 +93,8 @@ static void p2sb_configure_endpoints(int epmask_id, uint32_t mask)
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{
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uint32_t reg32;
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reg32 = pci_read_config32(P2SB_GET_DEV, PCH_P2SB_EPMASK(epmask_id));
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pci_write_config32(P2SB_GET_DEV, PCH_P2SB_EPMASK(epmask_id),
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reg32 = pci_read_config32(PCH_DEV_P2SB, PCH_P2SB_EPMASK(epmask_id));
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pci_write_config32(PCH_DEV_P2SB, PCH_P2SB_EPMASK(epmask_id),
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reg32 | mask);
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}
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@ -129,8 +103,8 @@ static void p2sb_lock_endpoints(void)
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uint8_t reg8;
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/* Set the "Endpoint Mask Lock!", P2SB PCI offset E2h bit[1] to 1. */
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reg8 = pci_read_config8(P2SB_GET_DEV, PCH_P2SB_E0 + 2);
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pci_write_config8(P2SB_GET_DEV, PCH_P2SB_E0 + 2,
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reg8 = pci_read_config8(PCH_DEV_P2SB, PCH_P2SB_E0 + 2);
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pci_write_config8(PCH_DEV_P2SB, PCH_P2SB_E0 + 2,
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reg8 | P2SB_E0_MASKLOCK);
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}
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