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soc/intel/meteorlake: Add entry for GSPI2 device 

This patch adds GSPI2 (PCI device B0:D18:F6) entry into the chipset.cb.

Additionally, increases `CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX` value
to include GSPI2 as well.

BUG=b:224325352
TEST=Able to build and boot Google/Rex platform.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I901128a1773fc6d2ba87e3e4972f45ad4a754d35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65675
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Subrata Banik 2022-07-06 12:54:48 +00:00 committed by Felix Held
parent f9a179a66d
commit e54a8fd432
2 changed files with 2 additions and 1 deletions
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2
src/soc/intel/meteorlake/Kconfig
View File

@ -208,7 +208,7 @@ config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
int
default 2
default 3
config SOC_INTEL_I2C_DEV_MAX
int

1
src/soc/intel/meteorlake/chipset.cb
View File

@ -81,6 +81,7 @@ chip soc/intel/meteorlake
device pci 10.0 alias thc0 off end
device pci 10.1 alias thc1 off end
device pci 12.0 alias ish off end
device pci 12.6 alias gspi2 off end
device pci 12.7 alias ufs off end
device pci 13.0 alias ioe_p2sb hidden end
device pci 13.1 alias ieh2 off end