mb/ocp/monolake: add TPM and IPMI support
Changes includes: - enable TPM1 + add entry in devicetree - configure LPC IO to make IPMI work + add entry in devicetree - introduce DSDT and SMBIOS entries for IPMI to make it detectable by ipmi_si driver Signed-off-by: Lukasz Siudut <lsiudut@fb.com> Change-Id: Ia975643064075f1f861f4ead6f24ed71f345ea04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
This commit is contained in:
Lukasz Siudut
Philipp Deppenwiese
parent
e7168edeb8
commit
e54c15aa72
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@ -11,6 +11,11 @@ config BOARD_SPECIFIC_OPTIONS
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select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
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select SERIRQ_CONTINUOUS_MODE
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select MAINBOARD_USES_IFD_GBE_REGION
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select MAINBOARD_HAS_LPC_TPM
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select MAINBOARD_HAS_TPM1
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config INTEGRATED_UART
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def_bool n
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config MAINBOARD_DIR
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string
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@ -7,7 +7,14 @@ chip soc/intel/fsp_broadwell_de
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device pci 14.0 on end # xHCI Controller
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device pci 19.0 on end # Gigabit LAN Controller
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device pci 1d.0 on end # EHCI Controller
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device pci 1f.0 on end # LPC Bridge
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device pci 1f.0 on
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chip drivers/pc80/tpm
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device pnp 0c31.0 on end
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end
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chip drivers/generic/generic # BMC KCS
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device pnp ca2.0 on end
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end
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end # LPC Bridge
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device pci 1f.2 on end # SATA Controller
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device pci 1f.3 on end # SMBus Controller
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device pci 1f.5 on end # SATA Controller
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@ -27,6 +27,9 @@ DefinitionBlock(
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{
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#include "acpi/platform.asl"
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Name (IDTP, 0x0CA2)
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Name (ICDP, 0x0CA6)
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Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 })
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Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 })
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@ -290,5 +293,97 @@ DefinitionBlock(
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}
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}
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Scope (_SB.PCI0.LPC0)
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{
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Device (SPMI)
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{
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Name (_HID, EisaId ("IPI0001"))
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Name (_STR, Unicode ("IPMI_KCS"))
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Name (_UID, 0x00)
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OperationRegion (IPST, SystemIO, ICDP, 0x01)
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Field (IPST, ByteAcc, NoLock, Preserve)
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{
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STAS, 8
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}
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Method (_STA, 0, NotSerialized) {
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Return (0x0f)
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}
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Name (ICRS, ResourceTemplate ()
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{
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IO (Decode16,
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0x0000,
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0x0000,
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0x00,
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0x00,
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_Y01)
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IO (Decode16,
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0x0000,
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0x0000,
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0x00,
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0x00,
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_Y02)
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})
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Method (_CRS, 0, NotSerialized)
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{
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CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._MIN, IPDB)
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CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._MAX, IPDH)
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CreateByteField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._LEN, IPDL)
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CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._MIN, IPCB)
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CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._MAX, IPCH)
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CreateByteField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._LEN, IPCL)
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IPDB = IDTP
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IPDH = IDTP
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IPDL = 0x01
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IPCB = ICDP
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IPCH = ICDP
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IPCL = 0x01
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Return (ICRS)
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}
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Method (_IFT, 0, NotSerialized) {
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Return (0x01)
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}
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Method(_SRV, 0, NotSerialized) {
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Return (0x0200)
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}
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}
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Device (SYSR)
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{
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Name (_HID, EisaId ("PNP0C02"))
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Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
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{
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IO (Decode16,
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0x0CA2,
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0x0CA2,
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0x01,
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0x01,
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)
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IO (Decode16,
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0x0CA6,
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0x0CA6,
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0x01,
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0x01,
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)
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IO (Decode16,
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0x0CA8,
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0x0CA8,
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0x01,
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0x01,
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)
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IO (Decode16,
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0x0CAC,
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0x0CAC,
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0x01,
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0x01,
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)
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})
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}
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}
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#include "acpi/mainboard.asl"
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}
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@ -15,17 +15,51 @@
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*/
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#include <device/device.h>
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#include <smbios.h>
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#if CONFIG(VGA_ROM_RUN)
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#include <x86emu/x86emu.h>
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#endif
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#define BMC_KCS_BASE 0xca2
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#define INTERFACE_IS_IO 0x1
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#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES)
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static int mainboard_smbios_data(struct device *dev, int *handle,
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unsigned long *current)
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{
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int len = 0;
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// add IPMI Device Information
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len += smbios_write_type38(
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current, handle,
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SMBIOS_BMC_INTERFACE_KCS,
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0x20, // IPMI Version
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0x20, // I2C address
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0xff, // no NV storage
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BMC_KCS_BASE | INTERFACE_IS_IO, // IO port interface address
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0x40,
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0); // no IRQ
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return len;
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}
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#endif
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/*
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* mainboard_enable is executed as first thing after enumerate_buses().
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* This is the earliest point to add customization.
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*/
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static void mainboard_enable(struct device *dev)
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{
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#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES)
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dev->ops->get_smbios_data = mainboard_smbios_data;
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#endif
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/* Enable access to the BMC IPMI via KCS */
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struct device *lpc_sio_dev = dev_find_slot_pnp(BMC_KCS_BASE, 0);
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struct resource *res = new_resource(lpc_sio_dev, BMC_KCS_BASE);
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res->base = BMC_KCS_BASE;
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res->size = 1;
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res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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}
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struct chip_operations mainboard_ops = {
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@ -20,6 +20,9 @@
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#include <cpu/x86/msr.h>
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#include <cf9_reset.h>
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#include <console/console.h>
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#include <device/pci_ops.h>
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#include <soc/pci_devs.h>
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#include <soc/lpc.h>
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/**
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* /brief mainboard call for setup that needs to be done before fsp init
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@ -49,7 +52,9 @@ void early_mainboard_romstage_entry(void)
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*/
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void late_mainboard_romstage_entry(void)
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{
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// IPMI through BIC
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pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN2_DEC,
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0x0c0ca1);
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}
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/**
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@ -57,5 +62,4 @@ void late_mainboard_romstage_entry(void)
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*/
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void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
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{
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}
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