intel/fsp_broadwell_de: Rename from xx_DEV_FUNC
Intel adopted xx_DEVFN_xx naming for macros expanding to PCI_DEVFN() starting with apollolake. The ones named xx_DEV_FUNC are being renamed, or dropped, if they were generally not used at all for a platform. Change-Id: I1a8675a4e613a8efc135b05cde36f166acaa7ed4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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@ -316,7 +316,7 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
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static unsigned long acpi_fill_dmar(unsigned long current)
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{
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uint32_t vtbar, tmp = current;
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struct device *dev = pcidev_path_on_root(VTD_DEV_FUNC);
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struct device *dev = pcidev_path_on_root(IIO_DEVFN_VTD);
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uint16_t bdf, hpet_bdf[8];
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uint8_t i, j;
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@ -333,7 +333,7 @@ static unsigned long acpi_fill_dmar(unsigned long current)
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current += acpi_create_dmar_ds_ioapic(current,
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9, 0, 5, 4);
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/* Get the PCI BDF for the PCH I/O APIC */
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dev = pcidev_path_on_root(LPC_DEV_FUNC);
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dev = pcidev_path_on_root(PCH_DEVFN_LPC);
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bdf = pci_read_config16(dev, 0x6c);
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current += acpi_create_dmar_ds_ioapic(current,
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8, (bdf >> 8), PCI_SLOT(bdf), PCI_FUNC(bdf));
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@ -24,7 +24,6 @@
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#define SOC_DEV 0
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#define SOC_FUNC 0
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#define SOC_DEV_FUNC PCI_DEVFN(SOC_DEV, SOC_FUNC)
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/* DMI2/PCIe link to PCH */
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#define PCIE_IIO_PORT_0_DEV 0x00
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@ -51,51 +50,42 @@
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#define VTD_DEV 5
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#define VTD_FUNC 0
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#define VTD_DEV_FUNC PCI_DEVFN(VTD_DEV, VTD_FUNC)
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#define IIO_DEVFN_VTD PCI_DEVFN(VTD_DEV, VTD_FUNC)
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#define VTD_PCI_DEV PCI_DEV(BUS0, VTD_DEV, VTD_FUNC)
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#define LPC_DEV 31
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#define LPC_FUNC 0
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#define LPC_DEV_FUNC PCI_DEVFN(LPC_DEV, LPC_FUNC)
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#define PCH_DEVFN_LPC PCI_DEVFN(LPC_DEV, LPC_FUNC)
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#define SATA_DEV 31
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#define SATA_FUNC 2
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#define SATA_DEV_FUNC PCI_DEVFN(SATA_DEV, SATA_FUNC)
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#define SMBUS_DEV 31
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#define SMBUS_FUNC 3
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#define SMBUS_DEV_FUNC PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC)
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#define SATA2_DEV 31
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#define SATA2_FUNC 5
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#define SATA2_DEV_FUNC PCI_DEVFN(SATA2_DEV, SATA2_FUNC)
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#define EHCI1_DEV 29
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#define EHCI1_FUNC 0
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#define EHCI1_DEV_FUNC PCI_DEVFN(EHCI_DEV1, EHCI_FUNC1)
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#define EHCI2_DEV 26
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#define EHCI2_FUNC 0
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#define EHCI2_DEV_FUNC PCI_DEVFN(EHCI_DEV2, EHCI_FUNC2)
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#define XHCI_DEV 20
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#define XHCI_FUNC 0
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#define XHCI_FUS_REG 0xE0
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#define XHCI_FUNC_DISABLE (1 << 0)
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#define XHCI_USB2PR_REG 0xD0
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#define XHCI_DEV_FUNC PCI_DEVFN(XHCI_DEV, XHCI_FUNC)
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#define GBE_DEV 25
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#define GBE_FUNC 0
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#define GBE_DEV_FUNC PCI_DEVFN(GBE_DEV, GBE_FUNC)
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#define ME_DEV 22
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#define ME_FUNC 0
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#define ME_DEV_FUNC PCI_DEVFN(ME_DEV, ME_FUNC)
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#define HDA_DEV 27
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#define HDA_FUNC 0
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#define HDA_DEV_FUNC PCI_DEVFN(HDA_DEV, HDA_FUNC)
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/* Ports from PCH block with adjustable burification settings */
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#define PCIE_DEV 28
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@ -115,20 +105,11 @@
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#define PCIE_PORT7_FUNC 6
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#define PCIE_PORT8_DEV PCIE_DEV
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#define PCIE_PORT8_FUNC 7
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#define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT1_FUNC)
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#define PCIE_PORT2_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT2_FUNC)
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#define PCIE_PORT3_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT3_FUNC)
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#define PCIE_PORT4_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT4_FUNC)
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#define PCIE_PORT5_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT5_FUNC)
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#define PCIE_PORT6_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT6_FUNC)
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#define PCIE_PORT7_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT7_FUNC)
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#define PCIE_PORT8_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT8_FUNC)
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/* The SMM device is located on bus 0xff (QPI) */
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#define QPI_BUS 0xff
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#define SMM_DEV 0x10
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#define SMM_FUNC 0x06
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#define SMM_DEV_FUNC PCI_DEVFN(SMM_DEV, SMM_FUNC)
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#define IMC_DEV0 19
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#define IMC_FUNC0 0
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@ -280,7 +280,7 @@ void southcluster_enable_dev(struct device *dev)
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#if CONFIG(HAVE_ACPI_TABLES)
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static const char *lpc_acpi_name(const struct device *dev)
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{
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if (dev->path.pci.devfn == LPC_DEV_FUNC)
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if (dev->path.pci.devfn == PCH_DEVFN_LPC)
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return "LPC0";
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else
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return NULL;
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