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intel/fsp_broadwell_de: Rename from xx_DEV_FUNC 

Intel adopted xx_DEVFN_xx naming for macros expanding to
PCI_DEVFN() starting with apollolake. The ones named
xx_DEV_FUNC are being renamed, or dropped, if they
were generally not used at all for a platform.

Change-Id: I1a8675a4e613a8efc135b05cde36f166acaa7ed4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This commit is contained in:
Kyösti Mälkki 2019-09-30 10:08:18 +03:00
parent 8d7a89b271
commit e552d073b7
3 changed files with 5 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/soc/intel/fsp_broadwell_de/acpi.c
View File

@ -316,7 +316,7 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
static unsigned long acpi_fill_dmar(unsigned long current) static unsigned long acpi_fill_dmar(unsigned long current)
{ {
uint32_t vtbar, tmp = current; uint32_t vtbar, tmp = current;
struct device *dev = pcidev_path_on_root(VTD_DEV_FUNC); struct device *dev = pcidev_path_on_root(IIO_DEVFN_VTD);
uint16_t bdf, hpet_bdf[8]; uint16_t bdf, hpet_bdf[8];
uint8_t i, j; uint8_t i, j;
@ -333,7 +333,7 @@ static unsigned long acpi_fill_dmar(unsigned long current)
current += acpi_create_dmar_ds_ioapic(current, current += acpi_create_dmar_ds_ioapic(current,
9, 0, 5, 4); 9, 0, 5, 4);
/* Get the PCI BDF for the PCH I/O APIC */ /* Get the PCI BDF for the PCH I/O APIC */
dev = pcidev_path_on_root(LPC_DEV_FUNC); dev = pcidev_path_on_root(PCH_DEVFN_LPC);
bdf = pci_read_config16(dev, 0x6c); bdf = pci_read_config16(dev, 0x6c);
current += acpi_create_dmar_ds_ioapic(current, current += acpi_create_dmar_ds_ioapic(current,
8, (bdf >> 8), PCI_SLOT(bdf), PCI_FUNC(bdf)); 8, (bdf >> 8), PCI_SLOT(bdf), PCI_FUNC(bdf));

23
src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h
View File

@ -24,7 +24,6 @@
#define SOC_DEV 0 #define SOC_DEV 0
#define SOC_FUNC 0 #define SOC_FUNC 0
#define SOC_DEV_FUNC PCI_DEVFN(SOC_DEV, SOC_FUNC)
/* DMI2/PCIe link to PCH */ /* DMI2/PCIe link to PCH */
#define PCIE_IIO_PORT_0_DEV 0x00 #define PCIE_IIO_PORT_0_DEV 0x00
@ -51,51 +50,42 @@
#define VTD_DEV 5 #define VTD_DEV 5
#define VTD_FUNC 0 #define VTD_FUNC 0
#define VTD_DEV_FUNC PCI_DEVFN(VTD_DEV, VTD_FUNC) #define IIO_DEVFN_VTD PCI_DEVFN(VTD_DEV, VTD_FUNC)
#define VTD_PCI_DEV PCI_DEV(BUS0, VTD_DEV, VTD_FUNC) #define VTD_PCI_DEV PCI_DEV(BUS0, VTD_DEV, VTD_FUNC)
#define LPC_DEV 31 #define LPC_DEV 31
#define LPC_FUNC 0 #define LPC_FUNC 0
#define LPC_DEV_FUNC PCI_DEVFN(LPC_DEV, LPC_FUNC) #define PCH_DEVFN_LPC PCI_DEVFN(LPC_DEV, LPC_FUNC)
#define SATA_DEV 31 #define SATA_DEV 31
#define SATA_FUNC 2 #define SATA_FUNC 2
#define SATA_DEV_FUNC PCI_DEVFN(SATA_DEV, SATA_FUNC)
#define SMBUS_DEV 31 #define SMBUS_DEV 31
#define SMBUS_FUNC 3 #define SMBUS_FUNC 3
#define SMBUS_DEV_FUNC PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC)
#define SATA2_DEV 31 #define SATA2_DEV 31
#define SATA2_FUNC 5 #define SATA2_FUNC 5
#define SATA2_DEV_FUNC PCI_DEVFN(SATA2_DEV, SATA2_FUNC)
#define EHCI1_DEV 29 #define EHCI1_DEV 29
#define EHCI1_FUNC 0 #define EHCI1_FUNC 0
#define EHCI1_DEV_FUNC PCI_DEVFN(EHCI_DEV1, EHCI_FUNC1)
#define EHCI2_DEV 26 #define EHCI2_DEV 26
#define EHCI2_FUNC 0 #define EHCI2_FUNC 0
#define EHCI2_DEV_FUNC PCI_DEVFN(EHCI_DEV2, EHCI_FUNC2)
#define XHCI_DEV 20 #define XHCI_DEV 20
#define XHCI_FUNC 0 #define XHCI_FUNC 0
#define XHCI_FUS_REG 0xE0 #define XHCI_FUS_REG 0xE0
#define XHCI_FUNC_DISABLE (1 << 0) #define XHCI_FUNC_DISABLE (1 << 0)
#define XHCI_USB2PR_REG 0xD0 #define XHCI_USB2PR_REG 0xD0
#define XHCI_DEV_FUNC PCI_DEVFN(XHCI_DEV, XHCI_FUNC)
#define GBE_DEV 25 #define GBE_DEV 25
#define GBE_FUNC 0 #define GBE_FUNC 0
#define GBE_DEV_FUNC PCI_DEVFN(GBE_DEV, GBE_FUNC)
#define ME_DEV 22 #define ME_DEV 22
#define ME_FUNC 0 #define ME_FUNC 0
#define ME_DEV_FUNC PCI_DEVFN(ME_DEV, ME_FUNC)
#define HDA_DEV 27 #define HDA_DEV 27
#define HDA_FUNC 0 #define HDA_FUNC 0
#define HDA_DEV_FUNC PCI_DEVFN(HDA_DEV, HDA_FUNC)
/* Ports from PCH block with adjustable burification settings */ /* Ports from PCH block with adjustable burification settings */
#define PCIE_DEV 28 #define PCIE_DEV 28
@ -115,20 +105,11 @@
#define PCIE_PORT7_FUNC 6 #define PCIE_PORT7_FUNC 6
#define PCIE_PORT8_DEV PCIE_DEV #define PCIE_PORT8_DEV PCIE_DEV
#define PCIE_PORT8_FUNC 7 #define PCIE_PORT8_FUNC 7
#define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT1_FUNC)
#define PCIE_PORT2_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT2_FUNC)
#define PCIE_PORT3_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT3_FUNC)
#define PCIE_PORT4_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT4_FUNC)
#define PCIE_PORT5_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT5_FUNC)
#define PCIE_PORT6_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT6_FUNC)
#define PCIE_PORT7_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT7_FUNC)
#define PCIE_PORT8_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT8_FUNC)
/* The SMM device is located on bus 0xff (QPI) */ /* The SMM device is located on bus 0xff (QPI) */
#define QPI_BUS 0xff #define QPI_BUS 0xff
#define SMM_DEV 0x10 #define SMM_DEV 0x10
#define SMM_FUNC 0x06 #define SMM_FUNC 0x06
#define SMM_DEV_FUNC PCI_DEVFN(SMM_DEV, SMM_FUNC)
#define IMC_DEV0 19 #define IMC_DEV0 19
#define IMC_FUNC0 0 #define IMC_FUNC0 0

2
src/soc/intel/fsp_broadwell_de/southcluster.c
View File

@ -280,7 +280,7 @@ void southcluster_enable_dev(struct device *dev)
#if CONFIG(HAVE_ACPI_TABLES) #if CONFIG(HAVE_ACPI_TABLES)
static const char *lpc_acpi_name(const struct device *dev) static const char *lpc_acpi_name(const struct device *dev)
{ {
if (dev->path.pci.devfn == LPC_DEV_FUNC) if (dev->path.pci.devfn == PCH_DEVFN_LPC)
return "LPC0"; return "LPC0";
else else
return NULL; return NULL;