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mb/google/sarien: Set minimum assertion width values 

Explicitly configure the minimum assertion width values to ensure
that they are set as expected and are not using unknown defaults.

Change-Id: I9a88e5b6002137df6e572b84d0de8a69522938f9
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
This commit is contained in:
Duncan Laurie 2019-01-07 12:09:55 -08:00 committed by Duncan Laurie
parent cae7944fc3
commit e55e61f889
2 changed files with 8 additions and 0 deletions
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4
src/mainboard/google/sarien/variants/arcada/devicetree.cb
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@ -23,6 +23,10 @@ chip soc/intel/cannonlake
register "InternalGfx" = "1" register "InternalGfx" = "1"
register "SkipExtGfxScan" = "1" register "SkipExtGfxScan" = "1"
register "VmxEnable" = "1" register "VmxEnable" = "1"
register "PchPmSlpS3MinAssert" = "3" # 50ms
register "PchPmSlpS4MinAssert" = "4" # 4s
register "PchPmSlpSusMinAssert" = "4" # 4s
register "PchPmSlpAMinAssert" = "4" # 2s
register "speed_shift_enable" = "1" register "speed_shift_enable" = "1"
register "s0ix_enable" = "1" register "s0ix_enable" = "1"

4
src/mainboard/google/sarien/variants/sarien/devicetree.cb
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@ -27,6 +27,10 @@ chip soc/intel/cannonlake
register "InternalGfx" = "1" register "InternalGfx" = "1"
register "SkipExtGfxScan" = "1" register "SkipExtGfxScan" = "1"
register "VmxEnable" = "1" register "VmxEnable" = "1"
register "PchPmSlpS3MinAssert" = "3" # 50ms
register "PchPmSlpS4MinAssert" = "4" # 4s
register "PchPmSlpSusMinAssert" = "4" # 4s
register "PchPmSlpAMinAssert" = "4" # 2s
register "speed_shift_enable" = "1" register "speed_shift_enable" = "1"
register "s0ix_enable" = "1" register "s0ix_enable" = "1"