mainboard/google/Kahlee: Select low-power mode for WiFi

Put the PCIe clock pins in power-saving mode for the WiFi module to save
power.

Note: This currently does not appear to have any effect on grunt.

BUG=b:110041917
BRANCH=none
TEST=boot without this patch:
$ iotools mem_read32 0xfed80e00
0x0046f3ff

With this patch:
$ iotools mem_read32 0xfed80e00
0x0046f3f1

Change-Id: I389815bc36b8610a30b0cbb9d73262ad392e0181
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/27465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

src/mainboard/google/kahlee/mainboard.c

@@ -150,6 +150,12 @@ static void mainboard_init(void *chip_info)
 			GPP_CLK2_CLOCK_REQ_MAP_MASK,
 			GPP_CLK2_CLOCK_REQ_MAP_CLK_REQ2 <<
 			GPP_CLK2_CLOCK_REQ_MAP_SHIFT);
+
+	/* Same for the WiFi */
+	clrsetbits_le32((uint32_t *)(MISC_MMIO_BASE + GPP_CLK_CNTRL),
+			GPP_CLK0_CLOCK_REQ_MAP_MASK,
+			GPP_CLK0_CLOCK_REQ_MAP_CLK_REQ0 <<
+			GPP_CLK0_CLOCK_REQ_MAP_SHIFT);
 }
 
 /*************************************************

src/soc/amd/stoneyridge/include/soc/southbridge.h

@@ -366,6 +366,10 @@
 #define GPP_CLK2_CLOCK_REQ_MAP_MASK	(0xf << GPP_CLK2_CLOCK_REQ_MAP_SHIFT)
 #define GPP_CLK2_CLOCK_REQ_MAP_CLK_REQ2	3
 
+#define GPP_CLK0_CLOCK_REQ_MAP_SHIFT	0
+#define GPP_CLK0_CLOCK_REQ_MAP_MASK	(0xf << GPP_CLK0_CLOCK_REQ_MAP_SHIFT)
+#define GPP_CLK0_CLOCK_REQ_MAP_CLK_REQ0	1
+
 struct stoneyridge_aoac {
 	int enable;
 	int status;