mainboard/google/Kahlee: Select low-power mode for WiFi
Put the PCIe clock pins in power-saving mode for the WiFi module to save power. Note: This currently does not appear to have any effect on grunt. BUG=b:110041917 BRANCH=none TEST=boot without this patch: $ iotools mem_read32 0xfed80e00 0x0046f3ff With this patch: $ iotools mem_read32 0xfed80e00 0x0046f3f1 Change-Id: I389815bc36b8610a30b0cbb9d73262ad392e0181 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/27465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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@ -150,6 +150,12 @@ static void mainboard_init(void *chip_info)
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GPP_CLK2_CLOCK_REQ_MAP_MASK,
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GPP_CLK2_CLOCK_REQ_MAP_MASK,
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GPP_CLK2_CLOCK_REQ_MAP_CLK_REQ2 <<
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GPP_CLK2_CLOCK_REQ_MAP_CLK_REQ2 <<
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GPP_CLK2_CLOCK_REQ_MAP_SHIFT);
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GPP_CLK2_CLOCK_REQ_MAP_SHIFT);
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/* Same for the WiFi */
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clrsetbits_le32((uint32_t *)(MISC_MMIO_BASE + GPP_CLK_CNTRL),
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GPP_CLK0_CLOCK_REQ_MAP_MASK,
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GPP_CLK0_CLOCK_REQ_MAP_CLK_REQ0 <<
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GPP_CLK0_CLOCK_REQ_MAP_SHIFT);
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}
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}
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/*************************************************
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/*************************************************
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@ -366,6 +366,10 @@
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#define GPP_CLK2_CLOCK_REQ_MAP_MASK (0xf << GPP_CLK2_CLOCK_REQ_MAP_SHIFT)
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#define GPP_CLK2_CLOCK_REQ_MAP_MASK (0xf << GPP_CLK2_CLOCK_REQ_MAP_SHIFT)
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#define GPP_CLK2_CLOCK_REQ_MAP_CLK_REQ2 3
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#define GPP_CLK2_CLOCK_REQ_MAP_CLK_REQ2 3
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#define GPP_CLK0_CLOCK_REQ_MAP_SHIFT 0
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#define GPP_CLK0_CLOCK_REQ_MAP_MASK (0xf << GPP_CLK0_CLOCK_REQ_MAP_SHIFT)
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#define GPP_CLK0_CLOCK_REQ_MAP_CLK_REQ0 1
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struct stoneyridge_aoac {
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struct stoneyridge_aoac {
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int enable;
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int enable;
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int status;
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int status;
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