tegra124: clock: Enforce PLL constraints for VCO and CF
This patch adds some documentation to the additional PLL divisor constraints on the intermediary VCO and CF values that we just found out about. PLLC divisors for some oscillators had to be adjusted accordingly. It also adds a new clock_get_pll_input_khz() function to replace clock_get_osc_khz() in cases where you want to factor in the built-in predivider for 38.4 and 48 MHz oscillators. BUG=None TEST=Still boots. Original-Change-Id: Ib6e026dbab9fcc50d6d81a884774ad07c7b0dbc3 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/194474 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 3f1f565baf100edcd486055e4317c675c882396f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I091f42bf952a4b58ef2c30586baa5bf7496fa599 Reviewed-on: http://review.coreboot.org/7768 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
This commit is contained in:
Julius Werner
Marc Jones
parent
d712ec47d4
commit
e57c303153
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@ -28,7 +28,7 @@
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void usb_setup_utmip(struct usb_ctlr *usb)
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{
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/* KHz formulas were guessed from U-Boot constants. Formats unclear. */
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int khz = clock_get_osc_khz();
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int khz = clock_get_pll_input_khz();
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/* Stop UTMI+ crystal clock while we mess with its settings */
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clrbits_le32(&usb->utmip.misc1, 1 << 30); /* PHY_XTAL_CLKEN */
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@ -325,15 +325,25 @@ check_member(clk_rst_ctlr, clk_src_soc_therm, 0x644);
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#define CPU0_CLK_STP_MASK (1U << CPU0_CLK_STP_SHIFT)
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/* CRC_OSC_CTRL_0 0x50 */
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#define OSC_CTRL_OSC_FREQ (0xf << 28)
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#define OSC_CTRL_OSC_FREQ_SHIFT 28
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#define OSC_FREQ_OSC13 0 /* 13.0MHz */
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#define OSC_FREQ_OSC19P2 4 /* 19.2MHz */
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#define OSC_FREQ_OSC12 8 /* 12.0MHz */
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#define OSC_FREQ_OSC26 12 /* 26.0MHz */
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#define OSC_FREQ_OSC16P8 1 /* 16.8MHz */
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#define OSC_FREQ_OSC38P4 5 /* 38.4MHz */
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#define OSC_FREQ_OSC48 9 /* 48.0MHz */
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#define OSC_FREQ_SHIFT 28
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#define OSC_FREQ_MASK (0xf << OSC_FREQ_SHIFT)
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#define OSC_PREDIV_SHIFT 26
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#define OSC_PREDIV_MASK (0x3 << OSC_PREDIV_SHIFT)
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#define OSC_XOFS_SHIFT 4
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#define OSC_XOFS_MASK (0x3F << OSC_XOFS_SHIFT)
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#define OSC_DRIVE_STRENGTH 7
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#define OSC_XOBP (1 << 1)
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#define OSC_XOE (1 << 0)
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enum {
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OSC_FREQ_12 = 8, /* 12.0MHz */
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OSC_FREQ_13 = 0, /* 13.0MHz */
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OSC_FREQ_16P8 = 1, /* 16.8MHz */
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OSC_FREQ_19P2 = 4, /* 19.2MHz */
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OSC_FREQ_26 = 12, /* 26.0MHz */
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OSC_FREQ_38P4 = 5, /* 38.4MHz */
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OSC_FREQ_48 = 9, /* 48.0MHz */
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};
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/* CLK_RST_CONTROLLER_PLL*_BASE_0 */
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#define PLL_BASE_BYPASS (1U << 31)
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@ -409,16 +419,6 @@ check_member(clk_rst_ctlr, clk_src_soc_therm, 0x644);
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#define PLLX_IDDQ_SHIFT 3
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#define PLLX_IDDQ_MASK (1U << PLLX_IDDQ_SHIFT)
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/* CLK_RST_CONTROLLER_OSC_CTRL_0 0x50 */
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#define OSC_XOE_SHIFT 0
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#define OSC_XOE_MASK (1 << OSC_XOE_SHIFT)
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#define OSC_XOE_ENABLE (1 << OSC_XOE_SHIFT)
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#define OSC_XOBP_SHIFT 1
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#define OSC_XOBP_MASK (1U << OSC_XOBP_SHIFT)
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#define OSC_XOFS_SHIFT 4
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#define OSC_XOFS_MASK (0x3F << OSC_XOFS_SHIFT)
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#define OSC_DRIVE_STRENGTH 7
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#define CLK_DIVISOR_MASK (0xffff)
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#define CLK_SOURCE_SHIFT 29
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@ -81,75 +81,77 @@ union __attribute__((transparent_union)) pll_fields {
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/* This table defines the frequency dividers for every PLL to turn the external
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* OSC clock into the frequencies defined by TEGRA_PLL*_KHZ in soc/clock.h.
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* All PLLs have three dividers (N, M and P), with the governing formula for
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* the output frequency being OUT = (IN / m) * N / (2^P).
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* Yes, it really is one equation with three unknowns ... */
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* All PLLs have three dividers (n, m and p), with the governing formula for
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* the output frequency being CF = (IN / m), VCO = CF * n and OUT = VCO / (2^p).
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* All divisor configurations must meet the PLL's constraints for VCO and CF:
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* PLLX: 12 MHz < CF < 50 MHz, 700 MHz < VCO < 3000 MHz
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* PLLC: 12 MHz < CF < 50 MHz, 600 MHz < VCO < 1400 MHz
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* PLLM: 12 MHz < CF < 50 MHz, 400 MHz < VCO < 1066 MHz
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* PLLP: 1 MHz < CF < 6 MHz, 200 MHz < VCO < 700 MHz
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* PLLD: 1 MHz < CF < 6 MHz, 500 MHz < VCO < 1000 MHz
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* PLLU: 1 MHz < CF < 6 MHz, 480 MHz < VCO < 960 MHz
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* PLLDP: 12 MHz < CF < 38 MHz, 600 MHz < VCO < 1200 MHz
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* (values taken from Linux' drivers/clk/tegra/clk-tegra124.c). */
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struct {
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int khz;
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struct pllcx_dividers pllx; /* target: CONFIG_PLLX_KHZ */
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struct pllcx_dividers pllc; /* target: 600 MHz */
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/* PLLM is set up dynamically by clock_sdram(). */
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/* PLLP is hardwired to 408 MHz in HW (unless we set BASE_OVRD). */
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struct pllu_dividers pllu; /* target; 960 MHz */
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struct pllcx_dividers plldp; /* target; 270 MHz */
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/* Based on T124 TRM (to be updatd), PLLP is set to 408MHz in HW.
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* Unless configuring PLLP to a frequency other than 408MHz,
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* software configuration on PLLP is unneeded. */
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/* PLLDP treats p differently (OUT = VCO / (p + 1) for p < 6). */
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} static const osc_table[16] = {
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[OSC_FREQ_OSC12]{
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[OSC_FREQ_12]{
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.khz = 12000,
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.pllx = {.n = TEGRA_PLLX_KHZ / 12000, .m = 1, .p = 0},
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.pllc = {.n = 50, .m = 1, .p = 0},
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.pllu = {.n = 960, .m = 12, .p = 0, .cpcon = 12, .lfcon = 2},
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.plldp = {.n = 90, .m = 1, .p = 3},
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},
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[OSC_FREQ_OSC13]{
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[OSC_FREQ_13]{
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.khz = 13000,
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.pllx = {.n = TEGRA_PLLX_KHZ / 13000, .m = 1, .p = 0},
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.pllc = {.n = 231, .m = 5, .p = 0}, /* 600.6 MHz */
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.pllc = {.n = 46, .m = 1, .p = 0}, /* 598.0 MHz */
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.pllu = {.n = 960, .m = 13, .p = 0, .cpcon = 12, .lfcon = 2},
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.plldp = {.n = 83, .m = 1, .p = 3}, /* 269.75 MHz */
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.plldp = {.n = 83, .m = 1, .p = 3}, /* 269.8 MHz */
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},
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[OSC_FREQ_OSC16P8]{
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[OSC_FREQ_16P8]{
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.khz = 16800,
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.pllx = {.n = TEGRA_PLLX_KHZ / 16800, .m = 1, .p = 0},
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.pllc = {.n = 250, .m = 7, .p = 0},
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.pllc = {.n = 71, .m = 1, .p = 1}, /* 596.4 MHz */
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.pllu = {.n = 400, .m = 7, .p = 0, .cpcon = 5, .lfcon = 2},
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.plldp = {.n = 64, .m = 1, .p = 3}, /* 268.8 MHz */
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.plldp = {.n = 64, .m = 1, .p = 3}, /* 268.8 MHz */
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},
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[OSC_FREQ_OSC19P2]{
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[OSC_FREQ_19P2]{
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.khz = 19200,
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.pllx = {.n = TEGRA_PLLX_KHZ / 19200, .m = 1, .p = 0},
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.pllc = {.n = 125, .m = 4, .p = 0},
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.pllc = {.n = 62, .m = 1, .p = 1}, /* 595.2 MHz */
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.pllu = {.n = 200, .m = 4, .p = 0, .cpcon = 3, .lfcon = 2},
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.plldp = {.n = 56, .m = 1, .p = 3}, /* 270.75 MHz */
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.plldp = {.n = 56, .m = 1, .p = 3}, /* 268.8 MHz */
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},
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[OSC_FREQ_OSC26]{
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[OSC_FREQ_26]{
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.khz = 26000,
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.pllx = {.n = TEGRA_PLLX_KHZ / 26000, .m = 1, .p = 0},
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.pllc = {.n = 23, .m = 1, .p = 0}, /* 598 MHz */
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.pllc = {.n = 23, .m = 1, .p = 0}, /* 598.0 MHz */
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.pllu = {.n = 960, .m = 26, .p = 0, .cpcon = 12, .lfcon = 2},
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.plldp = {.n = 83, .m = 2, .p = 3}, /* 266.50 MHz */
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.plldp = {.n = 83, .m = 2, .p = 3}, /* 269.8 MHz */
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},
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[OSC_FREQ_OSC38P4]{
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/* These oscillators get predivided as PLL inputs... n/m/p divisors for
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* 38.4 should always match 19.2, and 48 should always match 12. */
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[OSC_FREQ_38P4]{
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.khz = 38400,
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/*
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* There is a predivide by 2 before this PLL. Its values
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* should match the 19.2MHz values.
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*/
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.pllx = {.n = TEGRA_PLLX_KHZ / 19200, .m = 1, .p = 0},
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.pllc = {.n = 125, .m = 4, .p = 0},
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.pllc = {.n = 62, .m = 1, .p = 1}, /* 595.2 MHz */
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.pllu = {.n = 200, .m = 4, .p = 0, .cpcon = 3, .lfcon = 2},
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.plldp = {.n = 56, .m = 2, .p = 3}, /* 268 MHz */
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.plldp = {.n = 56, .m = 1, .p = 3}, /* 268.8 MHz */
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},
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[OSC_FREQ_OSC48]{
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[OSC_FREQ_48]{
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.khz = 48000,
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/*
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* There is a predivide by 4 before this PLL. Its values
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* should match the 12MHz values.
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*/
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.pllx = {.n = TEGRA_PLLX_KHZ / 12000, .m = 1, .p = 0},
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.pllc = {.n = 50, .m = 1, .p = 0},
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.pllu = {.n = 960, .m = 12, .p = 0, .cpcon = 12, .lfcon = 2},
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.plldp = {.n = 90, .m = 4, .p = 3}, /* 264 MHz */
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.plldp = {.n = 90, .m = 1, .p = 3},
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},
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};
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@ -159,7 +161,7 @@ struct {
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*/
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static u32 clock_get_osc_bits(void)
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{
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return readl(&clk_rst->osc_ctrl) >> OSC_CTRL_OSC_FREQ_SHIFT;
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return (readl(&clk_rst->osc_ctrl) & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
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}
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int clock_get_osc_khz(void)
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@ -167,6 +169,14 @@ int clock_get_osc_khz(void)
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return osc_table[clock_get_osc_bits()].khz;
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}
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int clock_get_pll_input_khz(void)
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{
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u32 osc_ctrl = readl(&clk_rst->osc_ctrl);
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u32 osc_bits = (osc_ctrl & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
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u32 pll_ref_div = (osc_ctrl & OSC_PREDIV_MASK) >> OSC_PREDIV_SHIFT;
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return osc_table[osc_bits].khz >> pll_ref_div;
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}
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void clock_init_arm_generic_timer(void)
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{
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uint32_t freq = clock_get_osc_khz() * 1000;
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@ -225,7 +235,7 @@ static void init_pll(u32 *base, u32 *misc, const union pll_fields pll, u32 lock)
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static void init_utmip_pll(void)
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{
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int khz = clock_get_osc_khz();
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int khz = clock_get_pll_input_khz();
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/* Shut off PLL crystal clock while we mess with it */
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clrbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */
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@ -304,22 +314,12 @@ clock_display(u32 frequency)
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*/
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struct pllpad_dividers plld = { 0 };
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u32 ref = clock_get_osc_khz() * 1000, m, n;
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u32 ref = clock_get_pll_input_khz() * 1000, m, n;
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u32 cf, vco = frequency;
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const u32 max_m = 1 << 5, max_n = 1 << 10, mhz = 1000 * 1000,
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min_vco = 500 * mhz, max_vco = 1000 * mhz,
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min_cf = 1 * mhz, max_cf = 6 * mhz;
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/* TODO(hungte) Replace this by clock_get_pll_input_khz */
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switch (clock_get_osc_bits()) {
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case OSC_FREQ_OSC48:
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ref /= 4;
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break;
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case OSC_FREQ_OSC38P4:
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ref /= 2;
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break;
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}
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if (vco < min_vco || vco > max_vco) {
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printk(BIOS_ERR, "%s: VCO (%d) out of range. Cannot support.\n",
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__func__, vco);
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@ -278,6 +278,7 @@ enum clock_source { /* Careful: Not true for all sources, always check TRM! */
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#define TEGRA_PLLU_KHZ (960000)
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int clock_get_osc_khz(void);
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int clock_get_pll_input_khz(void);
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int clock_display(u32 frequency);
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void clock_early_uart(void);
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void clock_external_output(int clk_id);
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@ -570,7 +570,7 @@ void sdram_init(const struct sdram_params *param)
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struct tegra_emc_regs *emc = (struct tegra_emc_regs*)TEGRA_EMC_BASE;
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printk(BIOS_DEBUG, "Initializing SDRAM of type %d with %dKHz\n",
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param->MemoryType, clock_get_osc_khz() *
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param->MemoryType, clock_get_pll_input_khz() *
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param->PllMFeedbackDivider / param->PllMInputDivider /
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(1 + param->PllMSelectDiv2));
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if (param->MemoryType != NvBootMemoryType_Ddr3)
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