soc/amd/common: Show current SPI speeds and modes
This patch adds code to print the current SPI speeds for each of the 4 different speeds, Normal, Fast-read, Alt-mode, & TPM. It also displays the SPI mode and whether or not SPI100 mode is enabled. BUG=b:194919326 TEST: Display the speed, change speeds, show that new speeds are the expected values. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I7825a9337474c147b803c85c9af7f9dc24670459 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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@ -32,6 +32,12 @@ enum spi_read_mode {
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#define SPI100_ENABLE 0x20
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#define SPI100_ENABLE 0x20
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#define SPI_USE_SPI100 BIT(0)
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#define SPI_USE_SPI100 BIT(0)
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#define DECODE_SPI_MODE_BITS(x) ((x) & SPI_READ_MODE_MASK)
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#define DECODE_SPI_MODE_UPPER_BITS(x) ((DECODE_SPI_MODE_BITS(x) >> 28) & 0x06)
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#define DECODE_SPI_MODE_LOWER_BITS(x) ((DECODE_SPI_MODE_BITS(x) >> 18) & 0x01)
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#define DECODE_SPI_READ_MODE(x) (DECODE_SPI_MODE_UPPER_BITS(x) | \
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DECODE_SPI_MODE_LOWER_BITS(x))
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/* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */
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/* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */
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#define SPI100_SPEED_CONFIG 0x22
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#define SPI100_SPEED_CONFIG 0x22
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enum spi100_speed {
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enum spi100_speed {
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@ -53,6 +59,13 @@ enum spi100_speed {
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#define SPI_SPEED_CFG(n, f, a, t) (SPI_NORM_SPEED(n) | SPI_FAST_SPEED(f) | \
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#define SPI_SPEED_CFG(n, f, a, t) (SPI_NORM_SPEED(n) | SPI_FAST_SPEED(f) | \
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SPI_ALT_SPEED(a) | SPI_TPM_SPEED(t))
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SPI_ALT_SPEED(a) | SPI_TPM_SPEED(t))
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#define DECODE_SPEED_MASK 0x07
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#define DECODE_SPEED_MODE(x, shift) (((x) >> shift) & DECODE_SPEED_MASK)
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#define DECODE_SPI_NORMAL_SPEED(x) DECODE_SPEED_MODE(x, 12)
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#define DECODE_SPI_FAST_SPEED(x) DECODE_SPEED_MODE(x, 8)
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#define DECODE_SPI_ALT_SPEED(x) DECODE_SPEED_MODE(x, 4)
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#define DECODE_SPI_TPM_SPEED(x) DECODE_SPEED_MODE(x, 0)
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#define SPI100_HOST_PREF_CONFIG 0x2c
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#define SPI100_HOST_PREF_CONFIG 0x2c
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#define SPI_RD4DW_EN_HOST BIT(15)
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#define SPI_RD4DW_EN_HOST BIT(15)
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@ -91,6 +104,9 @@ void fch_spi_early_init(void);
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/* Set the SPI base address variable */
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/* Set the SPI base address variable */
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void spi_set_base(void *base);
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void spi_set_base(void *base);
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/* Show the SPI settings */
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void show_spi_speeds_and_modes(void);
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/* Get the SPI base address variable's value */
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/* Get the SPI base address variable's value */
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uintptr_t spi_get_bar(void);
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uintptr_t spi_get_bar(void);
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uint8_t spi_read8(uint8_t reg);
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uint8_t spi_read8(uint8_t reg);
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@ -10,6 +10,46 @@
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#include <soc/lpc.h>
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#include <soc/lpc.h>
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#include <stdint.h>
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#include <stdint.h>
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static const char *spi_speed_str[8] = {
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"66.66 Mhz",
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"33.33 MHz",
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"22.22 MHz",
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"16.66 MHz",
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"100 MHz",
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"800 KHz",
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"Invalid",
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"Invalid"
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};
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static const char *read_mode_str[8] = {
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"Normal Read (up to 33M)",
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"Reserved",
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"Dual IO (1-1-2)",
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"Quad IO (1-1-4)",
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"Dual IO (1-2-2)",
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"Quad IO (1-4-4)",
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"Normal Read (up to 66M)",
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"Fast Read"
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};
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void show_spi_speeds_and_modes(void)
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{
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uint16_t val16 = spi_read16(SPI100_SPEED_CONFIG);
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uint32_t val32 = spi_read32(SPI_CNTRL0);
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printk(BIOS_DEBUG, "SPI normal read speed: %s\n",
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spi_speed_str[DECODE_SPI_NORMAL_SPEED(val16)]);
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printk(BIOS_DEBUG, "SPI fast read speed: %s\n",
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spi_speed_str[DECODE_SPI_FAST_SPEED(val16)]);
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printk(BIOS_DEBUG, "SPI alt read speed: %s\n",
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spi_speed_str[DECODE_SPI_ALT_SPEED(val16)]);
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printk(BIOS_DEBUG, "SPI TPM read speed: %s\n",
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spi_speed_str[DECODE_SPI_TPM_SPEED(val16)]);
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printk(BIOS_DEBUG, "SPI100: %s\n",
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spi_read16(SPI100_ENABLE) & SPI_USE_SPI100 ? "Enabled" : "Disabled");
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printk(BIOS_DEBUG, "SPI Read Mode: %s\n", read_mode_str[DECODE_SPI_READ_MODE(val32)]);
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}
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static uint8_t lower_speed(uint8_t speed1, uint8_t speed2)
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static uint8_t lower_speed(uint8_t speed1, uint8_t speed2)
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{
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{
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uint8_t speeds[] = {SPI_SPEED_800K, SPI_SPEED_16M, SPI_SPEED_22M,
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uint8_t speeds[] = {SPI_SPEED_800K, SPI_SPEED_16M, SPI_SPEED_22M,
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