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soc/intel/icelake: Fix 16-bit read/write PCI_COMMAND register 

Change-Id: Ibe9752a3f09e8944f7fbcf385b83faae95a7cd9b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Elyes HAOUAS 2020-04-29 09:43:32 +02:00 committed by Patrick Georgi
parent a1c767a19b
commit e585f5b5cc
1 changed files with 5 additions and 6 deletions
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11
src/soc/intel/icelake/bootblock/pch.c
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@ -41,22 +41,21 @@
static void soc_config_pwrmbase(void) static void soc_config_pwrmbase(void)
{ {
uint32_t reg32; uint32_t reg32;
uint16_t reg16;
/* /*
* Assign Resources to PWRMBASE * Assign Resources to PWRMBASE
* Clear BIT 1-2 Command Register * Clear BIT 1-2 Command Register
*/ */
reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND); reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND);
reg32 &= ~(PCI_COMMAND_MEMORY); reg16 &= ~(PCI_COMMAND_MEMORY);
pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32); pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16);
/* Program PWRM Base */ /* Program PWRM Base */
pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
/* Enable Bus Master and MMIO Space */ /* Enable Bus Master and MMIO Space */
reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND); pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY);
reg32 |= PCI_COMMAND_MEMORY;
pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32);
/* Enable PWRM in PMC */ /* Enable PWRM in PMC */
reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL)); reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL));