soc/intel/icelake: Fix 16-bit read/write PCI_COMMAND register
Change-Id: Ibe9752a3f09e8944f7fbcf385b83faae95a7cd9b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -41,22 +41,21 @@
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static void soc_config_pwrmbase(void)
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static void soc_config_pwrmbase(void)
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{
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{
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uint32_t reg32;
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uint32_t reg32;
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uint16_t reg16;
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/*
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/*
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* Assign Resources to PWRMBASE
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* Assign Resources to PWRMBASE
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* Clear BIT 1-2 Command Register
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* Clear BIT 1-2 Command Register
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*/
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*/
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reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND);
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reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND);
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reg32 &= ~(PCI_COMMAND_MEMORY);
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reg16 &= ~(PCI_COMMAND_MEMORY);
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pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32);
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pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16);
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/* Program PWRM Base */
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/* Program PWRM Base */
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pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
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pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
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/* Enable Bus Master and MMIO Space */
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/* Enable Bus Master and MMIO Space */
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reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND);
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pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY);
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reg32 |= PCI_COMMAND_MEMORY;
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pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32);
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/* Enable PWRM in PMC */
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/* Enable PWRM in PMC */
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reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL));
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reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL));
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