mb/google/brya: Create gaelin variant

Create the gaelin variant of the brask reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:239514438
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_GAELIN

Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Change-Id: I7f1ff8690c7c57f8960e004d0490d5cede8667f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>

src/mainboard/google/brya/Kconfig

@@ -216,6 +216,7 @@ config MAINBOARD_PART_NUMBER
 	default "Joxer" if BOARD_GOOGLE_JOXER
 	default "Pujjo" if BOARD_GOOGLE_PUJJO
 	default "Xivu" if BOARD_GOOGLE_XIVU
+	default "Gaelin4ADL" if BOARD_GOOGLE_GAELIN4ADL
 
 config VARIANT_DIR
 	default "brya0" if BOARD_GOOGLE_BRYA0
@@ -252,6 +253,7 @@ config VARIANT_DIR
 	default "joxer" if BOARD_GOOGLE_JOXER
 	default "pujjo" if BOARD_GOOGLE_PUJJO
 	default "xivu" if BOARD_GOOGLE_XIVU
+	default "gaelin" if BOARD_GOOGLE_GAELIN4ADL
 
 config VBOOT
 	select VBOOT_EARLY_EC_SYNC if !BOARD_GOOGLE_BASEBOARD_NISSA

src/mainboard/google/brya/Kconfig.name

@@ -270,3 +270,7 @@ config BOARD_GOOGLE_XIVU
 	select DRIVERS_GENERIC_GPIO_KEYS
 	select DRIVERS_GENESYSLOGIC_GL9750
 	select DRIVERS_INTEL_MIPI_CAMERA
+
+config BOARD_GOOGLE_GAELIN4ADL
+	bool "->  Gaelin4ADL"
+	select BOARD_GOOGLE_BASEBOARD_BRASK

src/mainboard/google/brya/variants/gaelin/include/variant/ec.h

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
+#include <baseboard/ec.h>
+
+#endif

src/mainboard/google/brya/variants/gaelin/include/variant/gpio.h

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif

src/mainboard/google/brya/variants/gaelin/overridetree.cb

@@ -0,0 +1,6 @@
+chip soc/intel/alderlake
+
+        device domain 0 on
+        end
+
+end