Initial IGD OpRegion implementation
Change-Id: I9e57c5792409830895a1147799acab95d910a336 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1757 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Stefan Reinauer
Stefan Reinauer
parent
2e200cde9a
commit
e5a0a5d6df
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@ -43,3 +43,5 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE),y)
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mrc.bin-position := 0xfffe0000
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endif
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mrc.bin-type := 0xab
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$(obj)/northbridge/intel/sandybridge/acpi.ramstage.o : $(obj)/build.h
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@ -2,6 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2012 The Chromium OS Authors
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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@ -22,11 +23,12 @@
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#include <types.h>
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#include <string.h>
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#include <console/console.h>
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#include <arch/io.h>
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#include <arch/acpi.h>
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#include <arch/acpigen.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <build.h>
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#include "sandybridge.h"
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unsigned long acpi_fill_mcfg(unsigned long current)
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@ -74,4 +76,127 @@ unsigned long acpi_fill_mcfg(unsigned long current)
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return current;
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}
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static void *get_intel_vbios(void)
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{
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/* This should probably be looking at CBFS or we should always
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* deploy the VBIOS on Intel systems, even if we don't run it
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* in coreboot (e.g. SeaBIOS only scenarios).
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*/
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u8 *vbios = (u8 *)0xc0000;
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optionrom_header_t *oprom = (optionrom_header_t *)vbios;
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optionrom_pcir_t *pcir = (optionrom_pcir_t *)(vbios +
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oprom->pcir_offset);
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printk(BIOS_DEBUG, "GET_VBIOS: %x %x %x %x %x\n",
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oprom->signature, pcir->vendor, pcir->classcode[0],
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pcir->classcode[1], pcir->classcode[2]);
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if ((oprom->signature == OPROM_SIGNATURE) &&
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(pcir->vendor == PCI_VENDOR_ID_INTEL) &&
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(pcir->classcode[0] == 0x00) &&
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(pcir->classcode[1] == 0x00) &&
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(pcir->classcode[2] == 0x03))
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return (void *)vbios;
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return NULL;
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}
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static int init_opregion_vbt(igd_opregion_t *opregion)
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{
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void *vbios;
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vbios = get_intel_vbios();
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if (!vbios) {
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printk(BIOS_DEBUG, "VBIOS not found.\n");
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return 1;
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}
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printk(BIOS_DEBUG, " ... VBIOS found at %p\n", vbios);
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optionrom_header_t *oprom = (optionrom_header_t *)vbios;
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optionrom_vbt_t *vbt = (optionrom_vbt_t *)(vbios +
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oprom->vbt_offset);
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if (read32((unsigned long)vbt->hdr_signature) != VBT_SIGNATURE) {
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printk(BIOS_DEBUG, "VBT not found!\n");
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return 1;
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}
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memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4);
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memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < 7168 ?
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vbt->hdr_vbt_size : 7168);
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return 0;
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}
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/* Initialize IGD OpRegion, called from ACPI code */
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int init_igd_opregion(igd_opregion_t *opregion)
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{
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device_t igd;
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u16 reg16;
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memset((void *)opregion, 0, sizeof(igd_opregion_t));
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// FIXME if IGD is disabled, we should exit here.
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memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
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sizeof(IGD_OPREGION_SIGNATURE));
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/* 8kb */
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opregion->header.size = sizeof(igd_opregion_t) / 1024;
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opregion->header.version = IGD_OPREGION_VERSION;
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// FIXME We just assume we're mobile for now
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opregion->header.mailboxes = MAILBOXES_MOBILE;
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// TODO Initialize Mailbox 1
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// TODO Initialize Mailbox 3
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opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
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opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
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opregion->mailbox3.pcft = 0; // should be (IMON << 1) & 0x3e
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opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;
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opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;
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opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;
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opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;
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opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;
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opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;
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opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;
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opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;
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opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;
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opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;
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opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;
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opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;
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init_opregion_vbt(opregion);
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/* TODO This needs to happen in S3 resume, too.
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* Maybe it should move to the finalize handler
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*/
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igd = dev_find_slot(0, PCI_DEVFN(0x2, 0));
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pci_write_config32(igd, ASLS, (u32)opregion);
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reg16 = pci_read_config16(igd, SWSCI);
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reg16 &= ~(1 << 0);
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reg16 |= (1 << 15);
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pci_write_config16(igd, SWSCI, reg16);
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/* clear dmisci status */
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reg16 = inw(DEFAULT_PMBASE + TCO1_STS);
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reg16 |= DMISCI_STS; // reference code does an &=
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outw(DEFAULT_PMBASE + TCO1_STS, reg16);
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/* clear acpi tco status */
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outl(DEFAULT_PMBASE + GPE0_STS, TCOSCI_STS);
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/* enable acpi tco scis */
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reg16 = inw(DEFAULT_PMBASE + GPE0_EN);
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reg16 |= TCOSCI_EN;
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outw(DEFAULT_PMBASE + GPE0_EN, reg16);
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return 0;
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}
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@ -0,0 +1,168 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Chromium OS Authors
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* mailbox 0: header */
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typedef struct {
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u8 signature[16];
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u32 size;
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u32 version;
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u8 sbios_version[32];
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u8 vbios_version[16];
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u8 driver_version[16];
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u32 mailboxes;
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u8 reserved[164];
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} __attribute__((packed)) opregion_header_t;
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#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem"
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#define IGD_OPREGION_VERSION 2
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#define IGD_MBOX1 (1 << 0)
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#define IGD_MBOX2 (1 << 1)
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#define IGD_MBOX3 (1 << 2)
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#define IGD_MBOX4 (1 << 3)
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#define IGD_MBOX5 (1 << 4)
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#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \
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IGD_MBOX4 | IGD_MBOX5)
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#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4)
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#define SBIOS_VERSION_SIZE 32
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/* mailbox 1: public acpi methods */
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typedef struct {
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u32 drdy;
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u32 csts;
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u32 cevt;
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u8 reserved1[20];
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u32 didl[8];
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u32 cpdl[8];
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u32 cadl[8];
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u32 nadl[8];
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u32 aslp;
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u32 tidx;
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u32 chpd;
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u32 clid;
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u32 cdck;
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u32 sxsw;
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u32 evts;
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u32 cnot;
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u32 nrdy;
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u8 reserved2[60];
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} __attribute__((packed)) opregion_mailbox1_t;
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/* mailbox 2: software sci interface */
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typedef struct {
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u32 scic;
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u32 parm;
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u32 dslp;
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u8 reserved[244];
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} __attribute__((packed)) opregion_mailbox2_t;
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/* mailbox 3: power conservation */
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typedef struct {
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u32 ardy;
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u32 aslc;
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u32 tche;
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u32 alsi;
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u32 bclp;
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u32 pfit;
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u32 cblv;
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u16 bclm[20];
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u32 cpfm;
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u32 epfm;
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u8 plut[74];
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u32 pfmb;
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u32 ccdv;
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u32 pcft;
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u8 reserved[94];
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} __attribute__((packed)) opregion_mailbox3_t;
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#define IGD_BACKLIGHT_BRIGHTNESS 0xff
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#define IGD_INITIAL_BRIGHTNESS 0x64
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#define IGD_FIELD_VALID (1 << 31)
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#define IGD_WORD_FIELD_VALID (1 << 15)
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#define IGD_PFIT_STRETCH 6
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/* mailbox 4: vbt */
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typedef struct {
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u8 gvd1[7168];
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} __attribute__((packed)) opregion_vbt_t;
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/* IGD OpRegion */
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typedef struct {
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opregion_header_t header;
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opregion_mailbox1_t mailbox1;
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opregion_mailbox2_t mailbox2;
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opregion_mailbox3_t mailbox3;
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opregion_vbt_t vbt;
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} __attribute__((packed)) igd_opregion_t;
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/* Intel Video BIOS (Option ROM) */
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typedef struct {
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u16 signature;
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u8 size;
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u8 reserved[21];
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u16 pcir_offset;
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u16 vbt_offset;
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} __attribute__((packed)) optionrom_header_t;
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#define OPROM_SIGNATURE 0xaa55
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typedef struct {
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u32 signature;
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u16 vendor;
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u16 device;
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u16 reserved1;
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u16 length;
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u8 revision;
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u8 classcode[3];
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u16 imagelength;
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u16 coderevision;
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u8 codetype;
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u8 indicator;
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u16 reserved2;
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} __attribute__((packed)) optionrom_pcir_t;
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typedef struct {
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u8 hdr_signature[20];
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u16 hdr_version;
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u16 hdr_size;
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u16 hdr_vbt_size;
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u8 hdr_vbt_checksum;
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u8 hdr_reserved;
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u32 hdr_vbt_datablock;
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u32 hdr_aim[4];
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u8 datahdr_signature[16];
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u16 datahdr_version;
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u16 datahdr_size;
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u16 datahdr_datablocksize;
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u8 coreblock_id;
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u16 coreblock_size;
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u16 coreblock_biossize;
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u8 coreblock_biostype;
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u8 coreblock_releasestatus;
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u8 coreblock_hwsupported;
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u8 coreblock_integratedhw;
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u8 coreblock_biosbuild[4];
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u8 coreblock_biossignon[155];
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} __attribute__((packed)) optionrom_vbt_t;
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#define VBT_SIGNATURE 0x54425624
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@ -53,7 +53,7 @@
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#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
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#define DEFAULT_RCBABASE 0xfed1c000
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#include "../../../southbridge/intel/bd82x6x/pch.h"
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#include <southbridge/intel/bd82x6x/pch.h>
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/* Everything below this line is ignored in the DSDT */
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#ifndef __ACPI__
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@ -107,7 +107,8 @@
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/* Device 0:2.0 PCI configuration space (Graphics Device) */
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#define MSAC 0x62 /* Multi Size Aperture Control */
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#define SWSCI 0xe8 /* SWSCI enable */
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#define ASLS 0xfc /* OpRegion Base */
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/*
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* MCHBAR
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@ -233,6 +234,9 @@ struct mrc_data_container {
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struct mrc_data_container *find_current_mrc_cache(void);
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#if !defined(__PRE_RAM__)
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void update_mrc_cache(void);
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#include "gma.h"
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int init_igd_opregion(igd_opregion_t *igd_opregion);
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#endif
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#endif
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