mb/siemens/mc_ehl: Add new mainboard based on elkhartlake_crb
Add a new mainboard called mc_ehl which is based on Intel's 'elkhartlake_crb'. This commit simply copies the mainboard directory and adjusts the naming to match the new board's name. Follow-up commits will introduce the needed changes for the new mainboard. Change-Id: Ia7c0616098046d975aa698910ac81f435d7882cb Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This commit is contained in:
Werner Zeh
Patrick Georgi
parent
d19cc1119f
commit
e5a1fc788f
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@ -0,0 +1,50 @@
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if BOARD_SIEMENS_MC_EHL
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_32768
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select DRIVERS_I2C_HID
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select DRIVERS_INTEL_DPTF
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select DRIVERS_I2C_GENERIC
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select DRIVERS_SPI_ACPI
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select DRIVERS_USB_ACPI
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select EC_ACPI
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select HAVE_SPD_IN_CBFS
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select SOC_INTEL_ELKHARTLAKE
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config MAINBOARD_DIR
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string
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default "siemens/mc_ehl"
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config VARIANT_DIR
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string
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default "mc_ehl1" if BOARD_SIEMENS_MC_EHL
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config MAINBOARD_PART_NUMBER
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string
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default "MC EHL"
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config MAINBOARD_FAMILY
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string
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default "Siemens EHL"
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config DEVICETREE
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string
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default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
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config DIMM_SPD_SIZE
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int
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default 512
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config VBOOT
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select VBOOT_LID_SWITCH
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select VBOOT_MOCK_SECDATA if !MAINBOARD_HAS_TPM2
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config UART_FOR_CONSOLE
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int
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default 2 if INTEL_LPSS_UART_FOR_CONSOLE
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default 0
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endif
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@ -0,0 +1,2 @@
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config BOARD_SIEMENS_MC_EHL
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bool "MC EHL"
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@ -0,0 +1,15 @@
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## SPDX-License-Identifier: GPL-2.0-only
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subdirs-y += spd
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bootblock-y += bootblock.c
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romstage-y += romstage_fsp_params.c
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ramstage-y += mainboard.c
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subdirs-y += variants/baseboard
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
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subdirs-y += variants/$(VARIANT_DIR)
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@ -0,0 +1,5 @@
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Vendor name: Siemens
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Board name: MC EHL
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Category: misc
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ROM protocol: SPI
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ROM socketed: n
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@ -0,0 +1,14 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <baseboard/variants.h>
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#include <bootblock_common.h>
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#include <soc/gpio.h>
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void bootblock_mainboard_init(void)
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{
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const struct pad_config *pads;
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size_t num;
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pads = variant_early_gpio_table(&num);
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gpio_configure_pads(pads, num);
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}
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@ -0,0 +1,32 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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ACPI_DSDT_REV_2,
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20110725 /* OEM revision */
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)
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{
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#include <acpi/dsdt_top.asl>
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#include <soc/intel/common/block/acpi/acpi/platform.asl>
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/* global NVS and variables */
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#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
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/* CPU */
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#include <cpu/intel/common/acpi/cpu.asl>
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
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#include <soc/intel/elkhartlake/acpi/southbridge.asl>
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}
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}
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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}
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@ -0,0 +1,18 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <baseboard/variants.h>
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#include <device/device.h>
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#include <soc/gpio.h>
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static void mainboard_init(void *chip_info)
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{
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const struct pad_config *pads;
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size_t num;
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pads = variant_gpio_table(&num);
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gpio_configure_pads(pads, num);
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}
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struct chip_operations mainboard_ops = {
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.init = mainboard_init,
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};
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@ -0,0 +1,20 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <baseboard/variants.h>
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#include <soc/meminit.h>
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#include <soc/romstage.h>
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void mainboard_memory_init_params(FSPM_UPD *memupd)
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{
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static struct spd_info spd_info;
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const struct mb_cfg *board_cfg = variant_memcfg_config();
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/* TODO: Read the resistor strap to get number of memory segments */
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bool half_populated = false;
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/* Initialize spd information for LPDDR4x board */
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spd_info.read_type = READ_SPD_CBFS;
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spd_info.spd_spec.spd_index = 0x00;
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/* Initialize variant specific configurations */
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memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, half_populated);
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}
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@ -0,0 +1,3 @@
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## SPDX-License-Identifier: GPL-2.0-only
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SPD_SOURCES = mc_ehl # 0b000
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@ -0,0 +1,32 @@
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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@ -0,0 +1,32 @@
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23 11 11 0E 15 21 90 08 00 40 00 00 02 22 00 00
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00 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60
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04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 E1 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20
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20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef MAINBOARD_SPD_H
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#define MAINBOARD_SPD_H
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#include <stdint.h>
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#define RCOMP_TARGET_PARAMS 0x5
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void mainboard_fill_dq_map_ch0(u8 *dq_map_ptr);
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void mainboard_fill_dq_map_ch1(u8 *dq_map_ptr);
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void mainboard_fill_dqs_map_ch0(u8 *dqs_map_ptr);
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void mainboard_fill_dqs_map_ch1(u8 *dqs_map_ptr);
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void mainboard_fill_rcomp_res_data(u16 *rcomp_ptr);
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void mainboard_fill_rcomp_strength_data(u16 *rcomp_strength_ptr);
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#endif
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@ -0,0 +1,18 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __BASEBOARD_VARIANTS_H__
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#define __BASEBOARD_VARIANTS_H__
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#include <soc/gpio.h>
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#include <soc/meminit.h>
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#include <stdint.h>
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/* The following 2 functions return the gpio table and fill in the number
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* of entries for each table. */
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const struct pad_config *variant_gpio_table(size_t *num);
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const struct pad_config *variant_early_gpio_table(size_t *num);
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/* This function returns SPD related FSP-M mainboard configs */
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const struct mb_cfg *variant_memcfg_config(void);
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#endif /*__BASEBOARD_VARIANTS_H__ */
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@ -0,0 +1,5 @@
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## SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += gpio.c
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romstage-y += memory.c
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ramstage-y += gpio.c
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@ -0,0 +1,259 @@
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chip soc/intel/elkhartlake
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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register "pmc_gpe0_dw0" = "GPP_B"
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register "pmc_gpe0_dw1" = "GPP_F"
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register "pmc_gpe0_dw2" = "GPP_E"
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# Enable heci1 communication
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register "HeciEnabled" = "1"
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# FSP configuration
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register "SaGv" = "SaGv_Enabled"
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register "SmbusEnable" = "1"
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register "Heci2Enable" = "1"
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# Display related UPDs
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# Enable HPD for DDI ports C
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register "DdiPortCHpd" = "1"
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# Enable DDC for DDI ports C
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register "DdiPortCDdc" = "1"
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# USB related UPDs
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register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port1
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register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # USB2 WWAN
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register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Bluetooth
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register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # Type-C Port1
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register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port2
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register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port3
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register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port4
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register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USB3/2 Type A port2
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register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Type A port1
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register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Type A port2
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port1
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port2
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # USB3 WLAN
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # UNUSED
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# Skip the CPU repalcement check
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register "SkipCpuReplacementCheck" = "1"
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# PCIe root ports related UPDs
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register "PcieRpEnable[0]" = "1"
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register "PcieRpEnable[1]" = "1"
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register "PcieRpEnable[2]" = "1"
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register "PcieRpEnable[3]" = "1"
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register "PcieRpEnable[4]" = "1"
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register "PcieRpEnable[5]" = "1"
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register "PcieRpEnable[6]" = "1"
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register "PcieClkSrcUsage[0]" = "0x00"
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register "PcieClkSrcUsage[1]" = "0x06"
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register "PcieClkSrcUsage[2]" = "0x04"
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register "PcieClkSrcUsage[3]" = "0xFF"
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register "PcieClkSrcUsage[4]" = "0xFF"
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register "PcieClkSrcUsage[5]" = "0xFF"
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register "PcieClkSrcClkReq[0]" = "0x0"
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register "PcieClkSrcClkReq[1]" = "0x1"
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register "PcieClkSrcClkReq[2]" = "0x2"
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register "PcieClkSrcClkReq[3]" = "0x3"
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register "PcieClkSrcClkReq[4]" = "0x4"
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register "PcieClkSrcClkReq[5]" = "0x5"
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# Storage (SATA/SDCARD/EMMC) related UPDs
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register "SataSalpSupport" = "1"
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register "SataPortsEnable[0]" = "1"
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register "SataPortsEnable[1]" = "1"
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register "SataPortsDevSlp[0]" = "0"
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register "SataPortsDevSlp[1]" = "1"
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register "ScsEmmcHs400Enabled" = "1"
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register "ScsEmmcDdr50Enabled" = "1"
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register "SdCardPowerEnableActiveHigh" = "1"
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# LPSS Serial IO (I2C/UART/GSPI) related UPDs
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register "SerialIoI2cMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C2] = PchSerialIoPci,
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[PchSerialIoIndexI2C3] = PchSerialIoPci,
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[PchSerialIoIndexI2C4] = PchSerialIoPci,
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[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C6] = PchSerialIoPci,
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[PchSerialIoIndexI2C7] = PchSerialIoPci,
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}"
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register "SerialIoI2cPadsTermination" = "{
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[PchSerialIoIndexI2C0] = 1,
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[PchSerialIoIndexI2C1] = 1,
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[PchSerialIoIndexI2C2] = 1,
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[PchSerialIoIndexI2C3] = 1,
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[PchSerialIoIndexI2C4] = 1,
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[PchSerialIoIndexI2C5] = 1,
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[PchSerialIoIndexI2C6] = 1,
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[PchSerialIoIndexI2C7] = 1,
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}"
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register "SerialIoGSpiMode" = "{
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[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI1] = PchSerialIoHidden,
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[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
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}"
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register "SerialIoGSpiCsEnable" = "{
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[PchSerialIoIndexGSPI0] = 1,
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[PchSerialIoIndexGSPI1] = 1,
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[PchSerialIoIndexGSPI2] = 1,
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}"
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register "SerialIoGSpiCsMode" = "{
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[PchSerialIoIndexGSPI0] = 0,
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[PchSerialIoIndexGSPI1] = 0,
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[PchSerialIoIndexGSPI2] = 0,
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}"
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|
||||
register "SerialIoGSpiCsState" = "{
|
||||
[PchSerialIoIndexGSPI0] = 0,
|
||||
[PchSerialIoIndexGSPI1] = 0,
|
||||
[PchSerialIoIndexGSPI2] = 0,
|
||||
}"
|
||||
|
||||
register "SerialIoUartMode" = "{
|
||||
[PchSerialIoIndexUART0] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
|
||||
}"
|
||||
|
||||
register "SerialIoUartDmaEnable" = "{
|
||||
[PchSerialIoIndexUART0] = 1,
|
||||
[PchSerialIoIndexUART1] = 1,
|
||||
[PchSerialIoIndexUART2] = 1,
|
||||
}"
|
||||
|
||||
# TSN GBE related UPDs
|
||||
register "PchTsnGbeLinkSpeed" = "Tsn_2_5_Gbps"
|
||||
register "PchTsnGbeSgmiiEnable" = "1"
|
||||
|
||||
# GPIO for SD card detect
|
||||
register "sdcard_cd_gpio" = "GPP_G5"
|
||||
|
||||
register "common_soc_config" = "{
|
||||
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
|
||||
}"
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
device pci 02.0 on end # Integrated Graphics Device
|
||||
device pci 04.0 off end # SA Thermal device
|
||||
device pci 08.0 off end # GNA
|
||||
device pci 09.0 off end # CPU Intel Trace Hub
|
||||
|
||||
device pci 10.0 on end # I2C6
|
||||
device pci 10.1 on end # I2C7
|
||||
device pci 10.5 on end # Integrated Error Handler
|
||||
|
||||
device pci 11.0 off end # Intel PSE UART0
|
||||
device pci 11.1 off end # Intel PSE UART1
|
||||
device pci 11.2 off end # Intel PSE UART2
|
||||
device pci 11.3 off end # Intel PSE UART3
|
||||
device pci 11.4 off end # Intel PSE UART4
|
||||
device pci 11.5 off end # Intel PSE UART5
|
||||
device pci 11.6 off end # Intel PSE IS20
|
||||
device pci 11.7 off end # Intel PSE IS21
|
||||
|
||||
device pci 12.0 on end # GSPI2
|
||||
device pci 12.3 on end # Management Engine UMA Access
|
||||
device pci 12.4 on end # Management Engine PTT DMA Controller
|
||||
device pci 12.5 off end # UFS0
|
||||
device pci 12.7 off end # UFS1
|
||||
|
||||
device pci 13.0 off end # Intel PSE GSPI0
|
||||
device pci 13.1 off end # Intel PSE GSPI1
|
||||
device pci 13.2 off end # Intel PSE GSPI2
|
||||
device pci 13.3 off end # Intel PSE GSPI3
|
||||
device pci 13.4 off end # Intel PSE GPIO0
|
||||
device pci 13.5 off end # Intel PSE GPIO1
|
||||
|
||||
device pci 14.0 on end # USB3.1 xHCI
|
||||
device pci 14.1 off end # USB3.1 xDCI (OTG)
|
||||
|
||||
device pci 15.0 on end # I2C0
|
||||
device pci 15.1 on end # I2C1
|
||||
device pci 15.2 on end # I2C2
|
||||
device pci 15.3 on end # I2C3
|
||||
|
||||
device pci 16.0 on end # Management Engine Interface 1
|
||||
device pci 16.1 on end # Management Engine Interface 2
|
||||
device pci 16.4 on end # Management Engine Interface 3
|
||||
device pci 16.5 on end # Management Engine Interface 4
|
||||
|
||||
device pci 17.0 on end # SATA
|
||||
|
||||
device pci 18.0 off end # Intel PSE I2C7
|
||||
device pci 18.1 off end # Intel PSE CAN0
|
||||
device pci 18.2 off end # Intel PSE CAN1
|
||||
device pci 18.3 off end # Intel PSE QEP0
|
||||
device pci 18.4 off end # Intel PSE QEP1
|
||||
device pci 18.5 off end # Intel PSE QEP2
|
||||
device pci 18.6 off end # Intel PSE QEP3
|
||||
|
||||
device pci 19.0 on end # I2C4
|
||||
device pci 19.1 on end # I2C5
|
||||
device pci 19.2 on end # UART2
|
||||
|
||||
device pci 1a.0 on end # eMMC
|
||||
device pci 1a.1 off end # SD
|
||||
device pci 1a.3 off end # Intel Safety Island
|
||||
|
||||
device pci 1b.0 off end # Intel PSE I2C0
|
||||
device pci 1b.1 off end # Intel PSE I2C1
|
||||
device pci 1b.2 off end # Intel PSE I2C2
|
||||
device pci 1b.3 off end # Intel PSE I2C3
|
||||
device pci 1b.4 off end # Intel PSE I2C4
|
||||
device pci 1b.5 off end # Intel PSE I2C5
|
||||
device pci 1b.6 off end # Intel PSE I2C6
|
||||
|
||||
device pci 1c.0 on end # RP1 (pcie0 single VC)
|
||||
device pci 1c.1 on end # RP2 (pcie0 single VC)
|
||||
device pci 1c.2 on end # RP3 (pcie0 single VC)
|
||||
device pci 1c.3 on end # RP4 (pcie0 single VC)
|
||||
device pci 1c.4 on end # RP5 (pcie1 multi VC)
|
||||
device pci 1c.5 on end # RP6 (pcie2 multi VC)
|
||||
device pci 1c.6 on end # RP7 (pcie3 multi VC)
|
||||
|
||||
device pci 1d.0 off end # Intel PSE IPC (local host to PSE)
|
||||
device pci 1d.1 on end # Intel PSE Time-Sensitive Networking GbE 0
|
||||
device pci 1d.2 on end # Intel PSE Time-Sensitive Networking GbE 1
|
||||
device pci 1d.3 off end # Intel PSE DMA0
|
||||
device pci 1d.4 off end # Intel PSE DMA1
|
||||
device pci 1d.5 off end # Intel PSE DMA2
|
||||
device pci 1d.6 off end # Intel PSE PWM
|
||||
device pci 1d.7 off end # Intel PSE ADC
|
||||
|
||||
device pci 1e.0 on end # UART0
|
||||
device pci 1e.1 on end # UART1
|
||||
device pci 1e.2 on end # GSPI0
|
||||
device pci 1e.3 on end # GSPI1
|
||||
device pci 1e.4 on end # PCH Time-Sensitive Networking GbE
|
||||
device pci 1e.6 on end # HPET
|
||||
device pci 1e.7 on end # IOAPIC
|
||||
|
||||
device pci 1f.0 on end # eSPI Interface
|
||||
device pci 1f.1 on end # P2SB
|
||||
device pci 1f.2 hidden end # Power Management Controller
|
||||
device pci 1f.3 off end # Intel cAVS/HDA
|
||||
device pci 1f.4 on end # SMBus
|
||||
device pci 1f.5 on end # PCH SPI (flash & TPM)
|
||||
device pci 1f.7 off end # PCH Intel Trace Hub
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,280 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <commonlib/helpers.h>
|
||||
|
||||
/* Pad configuration in ramstage*/
|
||||
static const struct pad_config gpio_table[] = {
|
||||
/*BT_RF_KILL_N*/
|
||||
PAD_CFG_GPO(GPP_E11, 1, DEEP),
|
||||
|
||||
/*WIFI_RF_KILL_N*/
|
||||
PAD_CFG_GPO(GPP_E10, 1, DEEP),
|
||||
|
||||
/*M.2_WLAN_PERST_N*/
|
||||
PAD_CFG_GPO(GPD7, 1, PLTRST),
|
||||
|
||||
/*M.2_WLAN_SLP*/
|
||||
PAD_CFG_GPO(GPD9, 1, PLTRST),
|
||||
|
||||
/*WIFI_WAKE_N*/
|
||||
PAD_CFG_GPI_SCI(GPP_F4, UP_5K, DEEP, LEVEL, INVERT),
|
||||
|
||||
/*UART_BT_WAKE_N*/
|
||||
PAD_CFG_GPI_SCI(GPP_F20, NONE, DEEP, LEVEL, INVERT),
|
||||
|
||||
/*ONBOARD_X4_PCIE_SLOT1_RESET_N*/
|
||||
PAD_CFG_GPO(GPD11, 1, PLTRST),
|
||||
|
||||
/*ONBOARD_X4_PCIE_SLOT1_WAKE_N*/
|
||||
PAD_CFG_GPI_SCI(GPP_E2, NONE, DEEP, LEVEL, INVERT),
|
||||
|
||||
/*M.2_WWAN_PWR_EN*/
|
||||
PAD_CFG_GPO(GPP_F21, 1, PLTRST),
|
||||
|
||||
/*M.2_WWAN_RST_N*/
|
||||
PAD_CFG_GPO(GPP_V13, 1, PLTRST),
|
||||
|
||||
/*M.2_WWAN_PE_RST_N*/
|
||||
PAD_CFG_GPO(GPP_B14, 1, PLTRST),
|
||||
|
||||
/*M.2_WWAN_PE_WAKE_N*/
|
||||
PAD_CFG_GPO(GPP_B17, 1, PLTRST),
|
||||
|
||||
/*M.2_WWAN_FCP_OFF_N*/
|
||||
PAD_CFG_GPO(GPP_E0, 1, PLTRST),
|
||||
|
||||
/*M.2_SSD_SATA_DEVSLP_1*/
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF2),
|
||||
|
||||
/*BC_PROCHOT_N*/
|
||||
PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT),
|
||||
|
||||
/*FPS_RST_N*/
|
||||
PAD_CFG_GPO(GPP_V14, 1, PLTRST),
|
||||
|
||||
/*FPS_INT*/
|
||||
PAD_CFG_GPI_APIC(GPP_V15, NONE, PLTRST, LEVEL, NONE),
|
||||
|
||||
/*CODEC_INT_N*/
|
||||
PAD_CFG_GPI(GPP_B15, NONE, PLTRST),
|
||||
|
||||
/*TCH_PNL_PWR_EN*/
|
||||
PAD_CFG_GPO(GPP_B16, 1, PLTRST),
|
||||
|
||||
/*THC0_SPI1_INT_N*/
|
||||
PAD_CFG_GPI_APIC(GPP_E17, NONE, PLTRST, LEVEL, INVERT),
|
||||
|
||||
/*SPI_TPM_INT_N*/
|
||||
PAD_CFG_GPI_APIC(GPP_G19, NONE, DEEP, LEVEL, NONE),
|
||||
|
||||
/*EMMC_CMD*/
|
||||
PAD_CFG_NF(GPP_V0, UP_20K, DEEP, NF1),
|
||||
|
||||
/*EMMC_DATA0*/
|
||||
PAD_CFG_NF(GPP_V1, UP_20K, DEEP, NF1),
|
||||
|
||||
/*EMMC_DATA1*/
|
||||
PAD_CFG_NF(GPP_V2, UP_20K, DEEP, NF1),
|
||||
|
||||
/*EMMC_DATA2*/
|
||||
PAD_CFG_NF(GPP_V3, UP_20K, DEEP, NF1),
|
||||
|
||||
/*EMMC_DATA3*/
|
||||
PAD_CFG_NF(GPP_V4, UP_20K, DEEP, NF1),
|
||||
|
||||
/*EMMC_DATA4*/
|
||||
PAD_CFG_NF(GPP_V5, UP_20K, DEEP, NF1),
|
||||
|
||||
/*EMMC_DATA5*/
|
||||
PAD_CFG_NF(GPP_V6, UP_20K, DEEP, NF1),
|
||||
|
||||
/*EMMC_DATA6*/
|
||||
PAD_CFG_NF(GPP_V7, UP_20K, DEEP, NF1),
|
||||
|
||||
/*EMMC_DATA7*/
|
||||
PAD_CFG_NF(GPP_V8, UP_20K, DEEP, NF1),
|
||||
|
||||
/*EMMC_RCLK*/
|
||||
PAD_CFG_NF(GPP_V9, DN_20K, DEEP, NF1),
|
||||
|
||||
/*EMMC_CLK*/
|
||||
PAD_CFG_NF(GPP_V10, DN_20K, DEEP, NF1),
|
||||
|
||||
/*EMMC_RESET*/
|
||||
PAD_CFG_NF(GPP_V11, UP_20K, DEEP, NF1),
|
||||
|
||||
/*ACPRESENT*/
|
||||
PAD_CFG_NF(GPD1, NONE, PLTRST, NF1),
|
||||
|
||||
/*RGMII0_MDC*/
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII0_MDIO*/
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII0_INT*/
|
||||
PAD_CFG_NF(GPP_T4, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII0_RESETB*/
|
||||
PAD_CFG_GPO(GPP_T5, 1, DEEP),
|
||||
|
||||
/*RGMII0_AUXTS*/
|
||||
PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII0_PPS*/
|
||||
PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII0_PPS*/
|
||||
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII0_PPS*/
|
||||
PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII0_PPS*/
|
||||
PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII0_PPS*/
|
||||
PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII0_PPS*/
|
||||
PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII0_PPS*/
|
||||
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII0_PPS*/
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII0_PPS*/
|
||||
PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII0_PPS*/
|
||||
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII0_PPS*/
|
||||
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII0_PPS*/
|
||||
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII0_PPS*/
|
||||
PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII1_MDC*/
|
||||
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII1_MDIO*/
|
||||
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII1_INT*/
|
||||
PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII1_RESETB*/
|
||||
PAD_CFG_GPO(GPP_H1, 1, DEEP),
|
||||
|
||||
/*RGMII1_AUXTS*/
|
||||
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII1_PPS*/
|
||||
PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII1_PPS*/
|
||||
PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII1_PPS*/
|
||||
PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII1_PPS*/
|
||||
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII1_PPS*/
|
||||
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII1_PPS*/
|
||||
PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII1_PPS*/
|
||||
PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII1_PPS*/
|
||||
PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII1_PPS*/
|
||||
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII1_PPS*/
|
||||
PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII1_PPS*/
|
||||
PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII1_PPS*/
|
||||
PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII1_PPS*/
|
||||
PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII2_MDC*/
|
||||
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII2_MDIO*/
|
||||
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII2_INT*/
|
||||
PAD_CFG_NF(GPP_U0, NONE, DEEP, NF1),
|
||||
|
||||
/*RGMII2_RESETB*/
|
||||
PAD_CFG_GPO(GPP_U1, 1, DEEP),
|
||||
};
|
||||
|
||||
/* Early pad configuration in bootblock */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
/* UART1 RX */
|
||||
PAD_CFG_NF(GPP_C12, NONE, DEEP, NF4),
|
||||
|
||||
/* UART1 TX */
|
||||
PAD_CFG_NF(GPP_C13, NONE, DEEP, NF4),
|
||||
|
||||
/* UART2 RX */
|
||||
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF4),
|
||||
|
||||
/* UART2 TX */
|
||||
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF4),
|
||||
|
||||
/*WWAN_FCP_OFF_N*/
|
||||
PAD_CFG_GPO(GPP_E0, 1, PLTRST),
|
||||
|
||||
/*WWAN_PWREN*/
|
||||
PAD_CFG_GPO(GPP_F21, 1, PLTRST),
|
||||
|
||||
/*WWAN_PERST_N*/
|
||||
PAD_CFG_GPO(GPP_B14, 0, PLTRST),
|
||||
|
||||
/*WWAN_RST_N*/
|
||||
PAD_CFG_GPO(GPP_V13, 0, PLTRST),
|
||||
|
||||
/* LAN_WAKEB*/
|
||||
PAD_CFG_GPI_SCI(GPD2, NONE, DEEP, EDGE_SINGLE, INVERT),
|
||||
|
||||
/*WWAN_RST_N*/
|
||||
PAD_CFG_GPO(GPP_V13, 0, PWROK),
|
||||
|
||||
/*WWAN_PERST_N*/
|
||||
PAD_CFG_GPO(GPP_B14, 0, PWROK),
|
||||
|
||||
/*WWAN_FCP_OFF_N*/
|
||||
PAD_CFG_GPO(GPP_E0, 0, PWROK),
|
||||
};
|
||||
|
||||
const struct pad_config *variant_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(gpio_table);
|
||||
return gpio_table;
|
||||
}
|
||||
|
||||
const struct pad_config *variant_early_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(early_gpio_table);
|
||||
return early_gpio_table;
|
||||
}
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <gpio.h>
|
||||
#include <soc/meminit.h>
|
||||
#include <soc/romstage.h>
|
||||
|
||||
static const struct mb_cfg mc_ehl_lpddr4x_memcfg_cfg = {
|
||||
|
||||
.dq_map[DDR_CH0] = {
|
||||
{0xf, 0xf0},
|
||||
{0xf, 0xf0},
|
||||
{0xff, 0x0},
|
||||
{0x0, 0x0},
|
||||
{0x0, 0x0},
|
||||
{0x0, 0x0}
|
||||
},
|
||||
|
||||
.dq_map[DDR_CH1] = {
|
||||
{0xf, 0xf0},
|
||||
{0xf, 0xf0},
|
||||
{0xff, 0x0},
|
||||
{0x0, 0x0},
|
||||
{0x0, 0x0},
|
||||
{0x0, 0x0}
|
||||
},
|
||||
|
||||
/*
|
||||
* The dqs_map arrays map the ddr4 pins to the SoC pins
|
||||
* for both channels.
|
||||
*
|
||||
* the index = pin number on ddr4 part
|
||||
* the value = pin number on SoC
|
||||
*/
|
||||
.dqs_map[DDR_CH0] = {3, 0, 1, 2, 7, 4, 5, 6},
|
||||
.dqs_map[DDR_CH1] = {3, 0, 1, 2, 7, 4, 5, 6},
|
||||
|
||||
/* Baseboard uses 100, 100 and 100 rcomp resistors */
|
||||
.rcomp_resistor = {100, 100, 100},
|
||||
|
||||
.rcomp_targets = {60, 40, 30, 20, 30},
|
||||
|
||||
/* LPDDR4x does not allow interleaved memory */
|
||||
.dq_pins_interleaved = 0,
|
||||
|
||||
/* Baseboard is using config 2 for vref_ca */
|
||||
.vref_ca_config = 2,
|
||||
|
||||
/* Enable Early Command Training */
|
||||
.ect = 1,
|
||||
|
||||
/* Set Board Type */
|
||||
.UserBd = BOARD_TYPE_MOBILE,
|
||||
};
|
||||
|
||||
const struct mb_cfg *variant_memcfg_config(void)
|
||||
{
|
||||
return &mc_ehl_lpddr4x_memcfg_cfg;
|
||||
}
|
||||
Loading…
Reference in New Issue