diff --git a/src/mainboard/google/poppy/variants/nautilus/Makefile.inc b/src/mainboard/google/poppy/variants/nautilus/Makefile.inc index a4f4165aa8..2167282cc8 100644 --- a/src/mainboard/google/poppy/variants/nautilus/Makefile.inc +++ b/src/mainboard/google/poppy/variants/nautilus/Makefile.inc @@ -9,3 +9,4 @@ romstage-y += memory.c ramstage-y += gpio.c ramstage-y += nhlt.c +ramstage-y += mainboard.c diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 79bb5fbe27..8de2413fcf 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -177,7 +177,7 @@ chip soc/intel/skylake register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 2 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port - register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # LTE module # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/poppy/variants/nautilus/gpio.c b/src/mainboard/google/poppy/variants/nautilus/gpio.c index b4db7ee198..b49665192e 100644 --- a/src/mainboard/google/poppy/variants/nautilus/gpio.c +++ b/src/mainboard/google/poppy/variants/nautilus/gpio.c @@ -16,6 +16,7 @@ #include #include #include +#include /* Pad configuration in ramstage */ /* Leave eSPI pins untouched from default settings */ @@ -49,8 +50,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* A17 : SD_PWR_EN# ==> CPU1_SDCARD_PWREN_L */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), - /* A18 : ISH_GP0 ==> NC */ - PAD_CFG_NC(GPP_A18), /* A19 : ISH_GP1 ==> NC */ PAD_CFG_NC(GPP_A19), /* A20 : ISH_GP2 ==> NC */ @@ -102,8 +101,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NC(GPP_B18), /* B19 : GSPI1_CS# ==> CHP3_PEN_EJECT - for notification */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B19, NONE, DEEP), - /* B20 : GSPI1_CLK ==> NC */ - PAD_CFG_NC(GPP_B20), + /* B20 : GSPI1_CLK ==> LTE3_STRAP# - for SAR sensor presence */ + PAD_CFG_GPI(GPP_B20, 20K_PD, DEEP), /* B21 : GSPI1_MISO ==> CHP3_PEN_EJECT - for wake event */ PAD_CFG_GPI_ACPI_SCI(GPP_B21, NONE, DEEP, NONE), /* B22 : GSPI1_MOSI ==> NC */ @@ -160,8 +159,6 @@ static const struct pad_config gpio_table[] = { /* C23 : UART2_CTS# ==> CHP3_PCH_WP*/ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), - /* D0 : SPI1_CS# ==> NC */ - PAD_CFG_NC(GPP_D0), /* D1 : SPI1_CLK ==> NC */ PAD_CFG_NC(GPP_D1), /* D2 : SPI1_MISO ==> NC */ @@ -192,8 +189,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NC(GPP_D14), /* D15 : ISH_UART0_RTS# ==> NC */ PAD_CFG_NC(GPP_D15), - /* D16 : ISH_UART0_CTS# ==> NC */ - PAD_CFG_NC(GPP_D16), /* D17 : DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* D18 : DMIC_DATA1 */ @@ -202,8 +197,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* D20 : DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), - /* D21 : SPI1_IO2 ==> NC */ - PAD_CFG_NC(GPP_D21), /* D22 : SPI1_IO3 ==> CHP1_BOOT_BEEP_OVERRIDE */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* D23 : I2S_MCLK ==> CHP1_I2S_MCLK */ @@ -382,3 +375,42 @@ const struct pad_config *variant_early_gpio_table(size_t *num) *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +static const struct pad_config nautilus_default_sku_gpio_table[] = { + /* A18 : ISH_GP0 ==> NC */ + PAD_CFG_NC(GPP_A18), + /* D0 : SPI1_CS# ==> NC */ + PAD_CFG_NC(GPP_D0), + /* D16 : ISH_UART0_CTS# ==> NC */ + PAD_CFG_NC(GPP_D16), + /* D21 : SPI1_IO2 ==> NC */ + PAD_CFG_NC(GPP_D21), +}; + +static const struct pad_config lte_sku_gpio_table[] = { + /* A18 : ISH_GP0 ==> LTE1_P_SENSOR_INT_L */ + PAD_CFG_GPI_APIC(GPP_A18, NONE, DEEP), + /* D0 : SPI1_CS# ==> LTE_PWROFF# */ + PAD_CFG_GPO(GPP_D0, 1, DEEP), + /* D16 : ISH_UART0_CTS# ==> LTE3_W_DISABLE# */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* D21 : SPI1_IO2 ==> LTE3_BODY_SAR */ + PAD_CFG_GPO(GPP_D21, 0, DEEP), +}; + +const struct pad_config *variant_sku_gpio_table(size_t *num) +{ + uint32_t sku_id = variant_board_sku(); + const struct pad_config *board_gpio_tables; + switch (sku_id) { + case SKU_1_NAUTILUS_LTE: + *num = ARRAY_SIZE(lte_sku_gpio_table); + board_gpio_tables = lte_sku_gpio_table; + break; + default: + *num = ARRAY_SIZE(nautilus_default_sku_gpio_table); + board_gpio_tables = nautilus_default_sku_gpio_table; + break; + } + return board_gpio_tables; +} diff --git a/src/mainboard/google/poppy/variants/nautilus/include/variant/sku.h b/src/mainboard/google/poppy/variants/nautilus/include/variant/sku.h new file mode 100644 index 0000000000..c101451641 --- /dev/null +++ b/src/mainboard/google/poppy/variants/nautilus/include/variant/sku.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_SKU_H__ +#define __MAINBOARD_SKU_H__ + +#define SKU_UNKNOWN 0xFFFFFFFF +#define SKU_0_NAUTILUS 0x0000 +#define SKU_1_NAUTILUS_LTE 0x0001 + +#endif /* __MAINBOARD_SKU_H__ */ diff --git a/src/mainboard/google/poppy/variants/nautilus/mainboard.c b/src/mainboard/google/poppy/variants/nautilus/mainboard.c new file mode 100644 index 0000000000..b4ef1c29dc --- /dev/null +++ b/src/mainboard/google/poppy/variants/nautilus/mainboard.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +uint32_t variant_board_sku(void) +{ + static uint32_t sku_id = SKU_UNKNOWN; + + if (sku_id != SKU_UNKNOWN) + return sku_id; + + if (board_id() < 9) + sku_id = SKU_0_NAUTILUS; + else + sku_id = SKU_1_NAUTILUS_LTE; + + return sku_id; +} + +/* Override dev tree settings per board */ +void variant_devtree_update(void) +{ + uint32_t sku_id = variant_board_sku(); + struct device *root = SA_DEV_ROOT; + config_t *cfg = root->chip_info; + + switch (sku_id) { + case SKU_0_NAUTILUS: + /* Disable LTE module */ + cfg->usb3_ports[3].enable = 0; + break; + + case SKU_1_NAUTILUS_LTE: + /* LTE board has different layout with Wifi sku, it need + new USB2 port strength settings */ + + /* Configure USB2 port 0 - USB2_PORT_TYPE_C(OC1) */ + cfg->usb2_ports[0].enable = 1; + cfg->usb2_ports[0].ocpin = OC1; + cfg->usb2_ports[0].tx_bias = USB2_BIAS_0MV; + cfg->usb2_ports[0].tx_emp_enable = USB2_PRE_EMP_ON; + cfg->usb2_ports[0].pre_emp_bias = USB2_BIAS_56MV; + cfg->usb2_ports[0].pre_emp_bit = USB2_HALF_BIT_PRE_EMP; + + /* Configure USB2 port 1 - USB2_PORT_LONG(OC2) */ + cfg->usb2_ports[1].enable = 1; + cfg->usb2_ports[1].ocpin = OC2; + cfg->usb2_ports[1].tx_bias = USB2_BIAS_39MV; + cfg->usb2_ports[1].tx_emp_enable = USB2_PRE_EMP_ON; + cfg->usb2_ports[1].pre_emp_bias = USB2_BIAS_56MV; + cfg->usb2_ports[1].pre_emp_bit = USB2_HALF_BIT_PRE_EMP; + + /* Configure USB2 port 4 - USB2_PORT_TYPE_C(OC0) */ + cfg->usb2_ports[4].enable = 1; + cfg->usb2_ports[4].ocpin = OC0; + cfg->usb2_ports[4].tx_bias = USB2_BIAS_0MV; + cfg->usb2_ports[4].tx_emp_enable = USB2_PRE_EMP_ON; + cfg->usb2_ports[4].pre_emp_bias = USB2_BIAS_56MV; + cfg->usb2_ports[4].pre_emp_bit = USB2_HALF_BIT_PRE_EMP; + break; + + default: + break; + } +}