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mainboard/msi/ms7d25: Configure NCT6687D pin for PECI 

One register configuring multi-pin functions was outside of the Global
Configuration Registers space and skipped in the initial port patches.

Replicate the vendor configuration and set the Super I/O pin for PECI
functionality.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I90f142a1a9ee27dd061fc71b791bd4c7df97da6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68711
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michał Żygowski 2022-10-23 12:07:58 +02:00 committed by Martin L Roth
parent 1864f12fda
commit e5b8a04f84
1 changed files with 9 additions and 1 deletions
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10
src/mainboard/msi/ms7d25/bootblock.c
View File

@ -6,6 +6,7 @@
#include <superio/nuvoton/nct6687d/nct6687d.h>
#define SERIAL_DEV PNP_DEV(0x4e, NCT6687D_SP1)
#define POWER_DEV PNP_DEV(0x4e, NCT6687D_SLEEP_PWR)
void bootblock_mainboard_early_init(void)
{
@ -13,6 +14,8 @@ void bootblock_mainboard_early_init(void)
nuvoton_pnp_enter_conf_state(SERIAL_DEV);
pnp_write_config(SERIAL_DEV, 0x13, 0xff); // IRQ8-15 level triggered, low
pnp_write_config(SERIAL_DEV, 0x14, 0xff); // IRQ0-7 level triggered, low
/* Below are multi-pin function */
pnp_write_config(SERIAL_DEV, 0x15, 0xaa);
pnp_write_config(SERIAL_DEV, 0x1a, 0x02);
pnp_write_config(SERIAL_DEV, 0x1b, 0x02);
@ -31,7 +34,12 @@ void bootblock_mainboard_early_init(void)
pnp_write_config(SERIAL_DEV, 0x2b, 0x20);
pnp_write_config(SERIAL_DEV, 0x2c, 0x8a);
pnp_write_config(SERIAL_DEV, 0x2d, 0xaa);
nuvoton_pnp_exit_conf_state(SERIAL_DEV);
pnp_set_logical_device(POWER_DEV);
/* Configure pin for PECI */
pnp_write_config(POWER_DEV, 0xf3, 0x80);
nuvoton_pnp_exit_conf_state(POWER_DEV);
if (CONFIG(CONSOLE_SERIAL))
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);