mb/51nb/x210/gpio: 4/4 Convert field macros to PAD_CFG
Converts bit fields macros to target PAD_CFG_*() macros. To do this, the following command was used: ./intelp2m -n -t 1 -file ../../src/mainboard/51nb/x210/gpio.h This is part of the patch set "mb/51nb/x210/gpio: Rewrite pad config using intelp2m": CB:43566 - 1/4 Decode raw register values CB:43567 - 2/4 Exclude fields for PAD_CFG CB:43568 - 3/4 Fixes PAD_RESET to convert to PAD_NC() CB:43410 - 4/4 Convert field macros to PAD_CFG Tested with BUILD_TIMELESS=1, 51NB-X210, remains identical. Change-Id: I18c0c321561eee04ff927681b0a231f6d79c63e2 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Maxim Polyakov
Patrick Georgi
parent
d09064e432
commit
e5b9dda758
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@ -6,174 +6,186 @@
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#include <soc/gpe.h>
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#include <soc/gpe.h>
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#include <soc/gpio.h>
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#include <soc/gpio.h>
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/*
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* Bidirectional GPIO port when both RX and TX buffer is enabled
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* todo: move this macros to src/soc/intel/common/block/include/intelblocks/gpio_defs.h
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*/
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#ifndef PAD_CFG_GPIO_BIDIRECT
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#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \
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_PAD_CFG_STRUCT(pad, \
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PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \
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PAD_BUF(NO_DISABLE) | val, \
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PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own))
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#endif
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#ifndef __ACPI__
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#ifndef __ACPI__
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/* Pad configuration in ramstage. */
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/* Pad configuration in ramstage. */
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static const struct pad_config gpio_table[] = {
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static const struct pad_config gpio_table[] = {
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/* RCIN# */_PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
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/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
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/* LAD0 */_PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(NATIVE)),
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/* LAD0 */ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
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/* LAD1 */_PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(NATIVE)),
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/* LAD1 */ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
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/* LAD2 */_PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(NATIVE)),
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/* LAD2 */ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
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/* LAD3 */_PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(NATIVE)),
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/* LAD3 */ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
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/* LFRAME# */_PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
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/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
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/* SERIRQ */_PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
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/* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
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/* GPIO */_PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),
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/* GPIO */ PAD_CFG_GPO(GPP_A7, 1, DEEP),
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/* GPIO */_PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PU)),
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/* GPIO */ PAD_NC(GPP_A8, 20K_PU),
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/* CLKOUT_LPC0 */_PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)),
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/* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1),
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/* CLKOUT_LPC1 */_PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)),
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/* CLKOUT_LPC1 */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1),
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/* GPIO */_PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
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/* GPIO */ PAD_CFG_GPO(GPP_A11, 0, DEEP),
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/* GPIO */_PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
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/* GPIO */ PAD_CFG_GPO(GPP_A12, 0, PWROK),
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/* SUSWARN#/SUSPWRDNACK */_PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
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/* SUSWARN#/SUSPWRDNACK */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
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/* SUS_STAT# */_PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
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/* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
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/* SUS_ACK# */_PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)),
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/* SUS_ACK# */ PAD_CFG_NF(GPP_A15, 20K_PU, DEEP, NF1),
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/* CLKOUT_48 */_PAD_CFG_STRUCT(GPP_A16, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
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/* CLKOUT_48 */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
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/* ISH_GP7 */_PAD_CFG_STRUCT(GPP_A17, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
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/* ISH_GP7 */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
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/* GPIO */_PAD_CFG_STRUCT(GPP_A18, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
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/* GPIO */ PAD_NC(GPP_A18, NONE),
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/* GPIO */_PAD_CFG_STRUCT(GPP_A19, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
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/* GPIO */ PAD_NC(GPP_A19, NONE),
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/* GPIO */_PAD_CFG_STRUCT(GPP_A20, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
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/* GPIO */ PAD_NC(GPP_A20, NONE),
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/* GPIO */_PAD_CFG_STRUCT(GPP_A21, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
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/* GPIO */ PAD_NC(GPP_A21, NONE),
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/* GPIO */_PAD_CFG_STRUCT(GPP_A22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),
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/* GPIO */ PAD_CFG_GPO(GPP_A22, 1, DEEP),
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/* GPIO */_PAD_CFG_STRUCT(GPP_A23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PD)),
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/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_A23, 20K_PD, DEEP, OFF, ACPI),
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/* n/a */_PAD_CFG_STRUCT(GPP_B0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
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/* n/a */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
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/* n/a */_PAD_CFG_STRUCT(GPP_B1, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
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/* n/a */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
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/* GPIO */_PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
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/* GPIO */ PAD_NC(GPP_B2, NONE),
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/* GPIO */_PAD_CFG_STRUCT(GPP_B3, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
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/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B3, NONE, PLTRST, OFF, ACPI),
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/* GPIO */_PAD_CFG_STRUCT(GPP_B4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),
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/* GPIO */ PAD_CFG_GPO(GPP_B4, 1, DEEP),
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/* SRCCLKREQ0# */_PAD_CFG_STRUCT(GPP_B5, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
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/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
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/* SRCCLKREQ1# */_PAD_CFG_STRUCT(GPP_B6, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
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/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
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/* SRCCLKREQ2# */_PAD_CFG_STRUCT(GPP_B7, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
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/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
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/* SRCCLKREQ3# */_PAD_CFG_STRUCT(GPP_B8, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
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/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
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/* SRCCLKREQ4# */_PAD_CFG_STRUCT(GPP_B9, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
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/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
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/* GPIO */_PAD_CFG_STRUCT(GPP_B10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
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/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, DEEP, OFF, ACPI),
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/* n/a */_PAD_CFG_STRUCT(GPP_B11, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
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/* n/a */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
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/* SLP_S0# */_PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
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/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
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/* PLTRST# */_PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
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/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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/* GPIO */_PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)),
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/* GPIO */ PAD_CFG_TERM_GPO(GPP_B14, 1, 20K_PD, DEEP),
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/* GPIO */_PAD_CFG_STRUCT(GPP_B15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
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/* GPIO */ PAD_NC(GPP_B15, NONE),
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/* GPIO */_PAD_CFG_STRUCT(GPP_B16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
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/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B16, NONE, PLTRST, OFF, ACPI),
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/* GPIO */_PAD_CFG_STRUCT(GPP_B17, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PU)),
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/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B17, 20K_PU, PLTRST, OFF, ACPI),
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/* GPIO */_PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PU)),
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/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B18, 20K_PU, PLTRST, OFF, ACPI),
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/* GPIO */_PAD_CFG_STRUCT(GPP_B19, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
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/* GPIO */ PAD_NC(GPP_B19, NONE),
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/* GSPI1_CLK */_PAD_CFG_STRUCT(GPP_B20, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)),
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/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1),
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/* GSPI1_MISO */_PAD_CFG_STRUCT(GPP_B21, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)),
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/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1),
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/* GSPIO_MOSI */_PAD_CFG_STRUCT(GPP_B22, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)),
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/* GSPIO_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1),
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/* GPIO */_PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)),
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/* GPIO */ PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PD, DEEP),
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/* SMBCLK */_PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
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/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
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/* SMBDATA */_PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)),
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/* SMBDATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1),
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/* GPIO */_PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)),
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/* GPIO */ PAD_CFG_TERM_GPO(GPP_C2, 1, 20K_PD, DEEP),
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/* SML0CLK */_PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)),
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/* SML0CLK */ PAD_CFG_NF(GPP_C3, 20K_PU, DEEP, NF1),
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/* SML0DATA */_PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)),
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/* SML0DATA */ PAD_CFG_NF(GPP_C4, 20K_PU, DEEP, NF1),
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/* GPIO */_PAD_CFG_STRUCT(GPP_C5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PD)),
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/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_C5, 20K_PD, DEEP, OFF, ACPI),
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/* RESERVED - GPP_C6 */
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/* RESERVED - GPP_C6 */
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/* RESERVED - GPP_C7 */
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/* RESERVED - GPP_C7 */
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/* UART0_RXD */_PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)),
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/* UART0_RXD */ PAD_CFG_NF(GPP_C8, 20K_PU, DEEP, NF1),
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/* UART0_TXD */_PAD_CFG_STRUCT(GPP_C9, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
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/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
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/* UART0_RTS# */_PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
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/* UART0_RTS# */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
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/* UART0_CTS# */_PAD_CFG_STRUCT(GPP_C11, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
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/* UART0_CTS# */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
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/* UART1_RXD */_PAD_CFG_STRUCT(GPP_C12, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
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/* UART1_RXD */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
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/* UART1_TXD */_PAD_CFG_STRUCT(GPP_C13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
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/* UART1_TXD */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
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/* UART1_RTS# */_PAD_CFG_STRUCT(GPP_C14, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
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/* UART1_RTS# */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
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/* UART1_CTS# */_PAD_CFG_STRUCT(GPP_C15, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
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/* UART1_CTS# */ PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1),
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/* I2C0_SDA */_PAD_CFG_STRUCT(GPP_C16, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)),
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/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 20K_PU, DEEP, NF1),
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/* I2C0_SCL */_PAD_CFG_STRUCT(GPP_C17, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)),
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/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 20K_PU, DEEP, NF1),
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/* I2C1_SDA */_PAD_CFG_STRUCT(GPP_C18, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)),
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/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, 20K_PU, DEEP, NF1),
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/* I2C1_SCL */_PAD_CFG_STRUCT(GPP_C19, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)),
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/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, 20K_PU, DEEP, NF1),
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/* UART2_RXD */_PAD_CFG_STRUCT(GPP_C20, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)),
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/* UART2_RXD */ PAD_CFG_NF(GPP_C20, 20K_PU, DEEP, NF1),
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/* UART2_TXD */_PAD_CFG_STRUCT(GPP_C21, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
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/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
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/* UART2_RTS# */_PAD_CFG_STRUCT(GPP_C22, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
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/* UART2_RTS# */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
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/* UART2_CTS# */_PAD_CFG_STRUCT(GPP_C23, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
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/* UART2_CTS# */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
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/* n/a */_PAD_CFG_STRUCT(GPP_D0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
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/* n/a */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1),
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/* n/a */_PAD_CFG_STRUCT(GPP_D1, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
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/* n/a */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
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/* n/a */_PAD_CFG_STRUCT(GPP_D2, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
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/* n/a */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1),
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/* n/a */_PAD_CFG_STRUCT(GPP_D3, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
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/* n/a */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1),
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/* ISH_I2C2_SDA */_PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
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/* ISH_I2C2_SDA */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
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/* I2S_SFRM */_PAD_CFG_STRUCT(GPP_D5, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)),
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/* I2S_SFRM */ PAD_CFG_NF(GPP_D5, 20K_PU, DEEP, NF1),
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/* I2S_TXD */_PAD_CFG_STRUCT(GPP_D6, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)),
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/* I2S_TXD */ PAD_CFG_NF(GPP_D6, 20K_PU, DEEP, NF1),
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/* I2S_RXD */_PAD_CFG_STRUCT(GPP_D7, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)),
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/* I2S_RXD */ PAD_CFG_NF(GPP_D7, 20K_PU, DEEP, NF1),
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/* I2S_SCLK */_PAD_CFG_STRUCT(GPP_D8, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)),
|
/* I2S_SCLK */ PAD_CFG_NF(GPP_D8, 20K_PU, DEEP, NF1),
|
||||||
/* GPIO */_PAD_CFG_STRUCT(GPP_D9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PU)),
|
/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D9, 20K_PU, DEEP, OFF, ACPI),
|
||||||
/* GPIO */_PAD_CFG_STRUCT(GPP_D10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PU)),
|
/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D10, 20K_PU, DEEP, OFF, ACPI),
|
||||||
/* GPIO */_PAD_CFG_STRUCT(GPP_D11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PU)),
|
/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D11, 20K_PU, DEEP, OFF, ACPI),
|
||||||
/* GPIO */_PAD_CFG_STRUCT(GPP_D12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PU)),
|
/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D12, 20K_PU, DEEP, OFF, ACPI),
|
||||||
/* ISH_UART0_RXD */_PAD_CFG_STRUCT(GPP_D13, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)),
|
/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, 20K_PU, DEEP, NF1),
|
||||||
/* ISH_UART0_TXD */_PAD_CFG_STRUCT(GPP_D14, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)),
|
/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, 20K_PU, DEEP, NF1),
|
||||||
/* ISH_UART0_RTS# */_PAD_CFG_STRUCT(GPP_D15, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* ISH_UART0_RTS# */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1),
|
||||||
/* ISH_UART0_CTS# */_PAD_CFG_STRUCT(GPP_D16, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* ISH_UART0_CTS# */ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
|
||||||
/* DMIC_CLK1 */_PAD_CFG_STRUCT(GPP_D17, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
|
||||||
/* DMIC_DATA1 */_PAD_CFG_STRUCT(GPP_D18, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)),
|
/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, 20K_PD, DEEP, NF1),
|
||||||
/* DMIC_CLK0 */_PAD_CFG_STRUCT(GPP_D19, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
|
||||||
/* DMIC_DATA0 */_PAD_CFG_STRUCT(GPP_D20, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)),
|
/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, 20K_PD, DEEP, NF1),
|
||||||
/* n/a */_PAD_CFG_STRUCT(GPP_D21, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* n/a */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
|
||||||
/* n/a */_PAD_CFG_STRUCT(GPP_D22, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* n/a */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
|
||||||
/* ISH_I2C2_SCL */_PAD_CFG_STRUCT(GPP_D23, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* ISH_I2C2_SCL */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
|
||||||
/* GPIO */_PAD_CFG_STRUCT(GPP_E0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
|
/* GPIO */ PAD_CFG_GPO(GPP_E0, 0, DEEP),
|
||||||
/* GPIO */_PAD_CFG_STRUCT(GPP_E1, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
|
/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E1, NONE, DEEP, OFF, ACPI),
|
||||||
/* GPIO */_PAD_CFG_STRUCT(GPP_E2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
|
/* GPIO */ PAD_NC(GPP_E2, NONE),
|
||||||
/* GPIO */_PAD_CFG_STRUCT(GPP_E3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
|
/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, OFF, ACPI),
|
||||||
/* GPIO */_PAD_CFG_STRUCT(GPP_E4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
|
/* GPIO */ PAD_NC(GPP_E4, NONE),
|
||||||
/* SATA_DEVSLP1 */_PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(NF1), 0),
|
/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, PWROK, NF1),
|
||||||
/* SATA_DEVSLP2 */_PAD_CFG_STRUCT(GPP_E6, PAD_FUNC(NF1), 0),
|
/* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, PWROK, NF1),
|
||||||
/* GPIO */_PAD_CFG_STRUCT(GPP_E7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
|
/* GPIO */ PAD_NC(GPP_E7, NONE),
|
||||||
/* SATA_LED# */_PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* SATA_LED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
|
||||||
/* USB_OC0# */_PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* USB_OC0# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
|
||||||
/* USB_OC1# */_PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* USB_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
|
||||||
/* USB_OC2# */_PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* USB_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
|
||||||
/* GPIO */_PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
|
/* GPIO */ PAD_NC(GPP_E12, NONE),
|
||||||
/* n/a */_PAD_CFG_STRUCT(GPP_E13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* n/a */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
|
||||||
/* n/a */_PAD_CFG_STRUCT(GPP_E14, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* n/a */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||||
/* GPIO */_PAD_CFG_STRUCT(GPP_E15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), 0),
|
/* GPIO */ PAD_CFG_GPI_SCI(GPP_E15, NONE, PLTRST, LEVEL, INVERT),
|
||||||
/* GPIO */_PAD_CFG_STRUCT(GPP_E16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
|
/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E16, NONE, PLTRST, OFF, ACPI),
|
||||||
/* n/a */_PAD_CFG_STRUCT(GPP_E17, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* n/a */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
|
||||||
/* n/a */_PAD_CFG_STRUCT(GPP_E18, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)),
|
/* n/a */ PAD_CFG_NF(GPP_E18, 20K_PU, DEEP, NF1),
|
||||||
/* n/a */_PAD_CFG_STRUCT(GPP_E19, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)),
|
/* n/a */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1),
|
||||||
/* n/a */_PAD_CFG_STRUCT(GPP_E20, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)),
|
/* n/a */ PAD_CFG_NF(GPP_E20, 20K_PU, DEEP, NF1),
|
||||||
/* n/a */_PAD_CFG_STRUCT(GPP_E21, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)),
|
/* n/a */ PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1),
|
||||||
/* GPIO */_PAD_CFG_STRUCT(GPP_E22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF), 0),
|
/* GPIO */ PAD_CFG_GPIO_BIDIRECT(GPP_E22, 0, NONE, DEEP, OFF, ACPI),
|
||||||
/* GPIO */_PAD_CFG_STRUCT(GPP_E23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)),
|
/* GPIO */ PAD_CFG_TERM_GPO(GPP_E23, 1, 20K_PD, DEEP),
|
||||||
/* BATLOW# */_PAD_CFG_STRUCT(GPD0, PAD_FUNC(NF1), PAD_PULL(20K_PU)),
|
/* BATLOW# */ PAD_CFG_NF(GPD0, 20K_PU, PWROK, NF1),
|
||||||
/* ACPRESENT */_PAD_CFG_STRUCT(GPD1, PAD_FUNC(NF1), 0),
|
/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, PWROK, NF1),
|
||||||
/* LAN_WAKE# */_PAD_CFG_STRUCT(GPD2, PAD_FUNC(NF1), PAD_PULL(NATIVE)),
|
/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1),
|
||||||
/* PWRBTN# */_PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1), PAD_PULL(20K_PU)),
|
/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, PWROK, NF1),
|
||||||
/* SLP_S3# */_PAD_CFG_STRUCT(GPD4, PAD_FUNC(NF1), 0),
|
/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
|
||||||
/* SLP_S4# */_PAD_CFG_STRUCT(GPD5, PAD_FUNC(NF1), 0),
|
/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
|
||||||
/* SLP_A# */_PAD_CFG_STRUCT(GPD6, PAD_FUNC(NF1), 0),
|
/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
|
||||||
/* GPIO */_PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),
|
/* GPIO */ PAD_NC(GPD7, NONE),
|
||||||
/* SUSCLK */_PAD_CFG_STRUCT(GPD8, PAD_FUNC(NF1), 0),
|
/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
|
||||||
/* SLP_WLAN# */_PAD_CFG_STRUCT(GPD9, PAD_FUNC(NF1), 0),
|
/* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, PWROK, NF1),
|
||||||
/* SLP_S5# */_PAD_CFG_STRUCT(GPD10, PAD_FUNC(NF1), 0),
|
/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
|
||||||
/* LANPHYPC */_PAD_CFG_STRUCT(GPD11, PAD_FUNC(NF1), 0),
|
/* LANPHYPC */ PAD_CFG_NF(GPD11, NONE, PWROK, NF1),
|
||||||
/* SATAXPCIE3 */_PAD_CFG_STRUCT(GPP_F0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* SATAXPCIE3 */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
|
||||||
/* SATAXPCIE4 */_PAD_CFG_STRUCT(GPP_F1, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* SATAXPCIE4 */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),
|
||||||
/* SATAXPCIE5 */_PAD_CFG_STRUCT(GPP_F2, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* SATAXPCIE5 */ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
|
||||||
/* SATAXPCIE6 */_PAD_CFG_STRUCT(GPP_F3, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* SATAXPCIE6 */ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1),
|
||||||
/* SATAXPCIE7 */_PAD_CFG_STRUCT(GPP_F4, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8 | PAD_PULL(20K_PU)),
|
/* SATAXPCIE7 */ PAD_CFG_NF_1V8(GPP_F4, 20K_PU, DEEP, NF1),
|
||||||
/* SATA_DEVSLP3 */_PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8 | PAD_PULL(20K_PU)),
|
/* SATA_DEVSLP3 */ PAD_CFG_NF_1V8(GPP_F5, 20K_PU, DEEP, NF1),
|
||||||
/* SATA_DEVSLP4 */_PAD_CFG_STRUCT(GPP_F6, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8 | PAD_PULL(20K_PU)),
|
/* SATA_DEVSLP4 */ PAD_CFG_NF_1V8(GPP_F6, 20K_PU, DEEP, NF1),
|
||||||
/* SATA_DEVSLP5 */_PAD_CFG_STRUCT(GPP_F7, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8 | PAD_PULL(20K_PU)),
|
/* SATA_DEVSLP5 */ PAD_CFG_NF_1V8(GPP_F7, 20K_PU, DEEP, NF1),
|
||||||
/* SATA_DEVSLP6 */_PAD_CFG_STRUCT(GPP_F8, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8 | PAD_PULL(20K_PU)),
|
/* SATA_DEVSLP6 */ PAD_CFG_NF_1V8(GPP_F8, 20K_PU, DEEP, NF1),
|
||||||
/* SATA_DEVSLP7 */_PAD_CFG_STRUCT(GPP_F9, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8 | PAD_PULL(20K_PU)),
|
/* SATA_DEVSLP7 */ PAD_CFG_NF_1V8(GPP_F9, 20K_PU, DEEP, NF1),
|
||||||
/* n/a */_PAD_CFG_STRUCT(GPP_F10, PAD_FUNC(NF2) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8 | PAD_PULL(20K_PU)),
|
/* n/a */ PAD_CFG_NF_1V8(GPP_F10, 20K_PU, DEEP, NF2),
|
||||||
/* n/a */_PAD_CFG_STRUCT(GPP_F11, PAD_FUNC(NF2) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8 | PAD_PULL(20K_PU)),
|
/* n/a */ PAD_CFG_NF_1V8(GPP_F11, 20K_PU, DEEP, NF2),
|
||||||
/* SATA_SDATAOUT1 */_PAD_CFG_STRUCT(GPP_F12, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* SATA_SDATAOUT1 */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
|
||||||
/* SATA_SDATAOUT2 */_PAD_CFG_STRUCT(GPP_F13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* SATA_SDATAOUT2 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
|
||||||
/* n/a */_PAD_CFG_STRUCT(GPP_F14, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* n/a */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
|
||||||
/* USB_OC4# */_PAD_CFG_STRUCT(GPP_F15, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* USB_OC4# */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
|
||||||
/* USB_OC5# */_PAD_CFG_STRUCT(GPP_F16, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* USB_OC5# */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
|
||||||
/* USB_OC6# */_PAD_CFG_STRUCT(GPP_F17, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* USB_OC6# */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
|
||||||
/* USB_OC7# */_PAD_CFG_STRUCT(GPP_F18, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* USB_OC7# */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
|
||||||
/* eDP_VDDEN */_PAD_CFG_STRUCT(GPP_F19, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* eDP_VDDEN */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||||
/* eDP_BKLTEN */_PAD_CFG_STRUCT(GPP_F20, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* eDP_BKLTEN */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
|
||||||
/* eDP_BKLTCTL */_PAD_CFG_STRUCT(GPP_F21, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* eDP_BKLTCTL */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
|
||||||
/* n/a */_PAD_CFG_STRUCT(GPP_F22, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* n/a */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
|
||||||
/* GPIO */_PAD_CFG_STRUCT(GPP_F23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
|
/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F23, NONE, DEEP, OFF, ACPI),
|
||||||
/* FAN_TACH_0 */_PAD_CFG_STRUCT(GPP_G0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* FAN_TACH_0 */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
|
||||||
/* FAN_TACH_1 */_PAD_CFG_STRUCT(GPP_G1, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* FAN_TACH_1 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
|
||||||
/* FAN_TACH_2 */_PAD_CFG_STRUCT(GPP_G2, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* FAN_TACH_2 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
|
||||||
/* FAN_TACH_3 */_PAD_CFG_STRUCT(GPP_G3, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* FAN_TACH_3 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
|
||||||
/* FAN_TACH_4 */_PAD_CFG_STRUCT(GPP_G4, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* FAN_TACH_4 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
|
||||||
/* FAN_TACH_5 */_PAD_CFG_STRUCT(GPP_G5, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* FAN_TACH_5 */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
|
||||||
/* FAN_TACH_6 */_PAD_CFG_STRUCT(GPP_G6, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
|
/* FAN_TACH_6 */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
|
||||||
/* FAN_TACH_7 */_PAD_CFG_STRUCT(GPP_G7, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)),
|
/* FAN_TACH_7 */ PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1),
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue