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soc/intel/common: Add support to read CPU and PCH Trace Hub modes 

The patch parses CPU and PCH Trace Hub modes from the debug area in the
Descriptor Region. The modes can be updated in the debug area in order
to configure the CPU and PCH Trace Hub modes. The debug area's offset
starts from the SPI Flash offset:0xf00.

For runtime debugging, the OEM Section in the Descriptor Region is being
used as debug area. The OEM Section details are documented in the SPI
Programmer Guide of CSE Lite kit.

TEST=Build code for Gimble

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I61241c5c1981ddc4b21581bb3ed9f531da5f41b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
This commit is contained in:
Sridhar Siricilla 2022-04-28 23:32:01 +05:30 committed by Felix Held
parent 88019ddbdf
commit e5ca71db06
2 changed files with 29 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
src/soc/intel/common/basecode/debug/debug_feature.c
View File

@ -9,9 +9,22 @@
#define DEBUG_FEATURE_CTRL_SZ 64 #define DEBUG_FEATURE_CTRL_SZ 64
#define SI_DESC_REGION_SZ 4096 #define SI_DESC_REGION_SZ 4096
#define DEBUG_FEATURE_UNDEFINED 0xff
struct debug_feature_cntrl { struct debug_feature_cntrl {
uint8_t cse_fw_update_disable; /* Byte location: 0xF00 */ uint8_t cse_fw_update_disable; /* Byte location: 0xF00 */
uint8_t reserved[63];
/*
* Supported CPU Trace Hub modes:
* 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode
*/
uint8_t cpu_tracehub_mode; /* Byte location: 0xF01 */
/*
* Supported PCH Trace Hub modes:
* 0: Disable, 1:Target Debugger Mode, 2:Host Debugger Mode
*/
uint8_t pch_tracehub_mode; /* Byte location: 0xF02 */
uint8_t reserved[61];
}; };
static struct debug_feature_cntrl dbg_feature_cntrl; static struct debug_feature_cntrl dbg_feature_cntrl;
@ -20,6 +33,18 @@ _Static_assert(sizeof(struct debug_feature_cntrl) % 64 == 0
&& sizeof(struct debug_feature_cntrl) <= 256, && sizeof(struct debug_feature_cntrl) <= 256,
"sizeof(struct debug_feature_cntrl) must be a multiple of 64 bytes and up to 256 bytes"); "sizeof(struct debug_feature_cntrl) must be a multiple of 64 bytes and up to 256 bytes");
void debug_get_pch_cpu_tracehub_modes(uint8_t *cpu_tracehub_mode, uint8_t *pch_tracehub_mode)
{
if (dbg_feature_cntrl.pch_tracehub_mode != DEBUG_FEATURE_UNDEFINED)
*pch_tracehub_mode = dbg_feature_cntrl.pch_tracehub_mode;
if (dbg_feature_cntrl.cpu_tracehub_mode != DEBUG_FEATURE_UNDEFINED)
*cpu_tracehub_mode = dbg_feature_cntrl.cpu_tracehub_mode;
printk(BIOS_DEBUG, "rt_debug: CPU Trace Hub Mode: %d PCH Trace Hub Mode: %d\n",
*pch_tracehub_mode, *cpu_tracehub_mode);
}
bool is_debug_cse_fw_update_disable(void) bool is_debug_cse_fw_update_disable(void)
{ {
printk(BIOS_DEBUG, "rt_debug: dbg_feature_cntrl.cse_fw_update_disable=%d\n", printk(BIOS_DEBUG, "rt_debug: dbg_feature_cntrl.cse_fw_update_disable=%d\n",

3
src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h
View File

@ -5,6 +5,9 @@
#include <types.h> #include <types.h>
/* Get cpu and pch tracehub modes defined in the OEM Section of descriptor region */
void debug_get_pch_cpu_tracehub_modes(uint8_t *cpu_tracehub_mode, uint8_t *pch_trachub_mode);
/* Check if CSE firmware update is enabled or not */ /* Check if CSE firmware update is enabled or not */
bool is_debug_cse_fw_update_disable(void); bool is_debug_cse_fw_update_disable(void);