soc/intel/skylake: Fix FSP1.1 booting issue with HW based dram top calculation
This patch ensures skylake device using FSP1.1 can use HW based DRAM top calculation which was broken due to skylake fsp1.1 not honoring any UPD to know PRMMR size and default reserving 1MB for PRMRR size. This WA is not needed for FSP2.0 implementation due to PrmrrSize UPD is available and considering into hw based dram top calculation. BRANCH=none BUG=b:63974384 TEST=Build and boot lars which is using skylake 1.1 fsp. Change-Id: Iade0d2cb2a290fc4c9f0e6b1eaadc8afff2fa581 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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@ -178,7 +178,10 @@ static u32 calculate_dram_base(void)
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dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_ROOT, 0));
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config = dev->chip_info;
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prmrr_size = config->PrmrrSize;
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if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1))
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prmrr_size = 1*MiB;
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else
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prmrr_size = config->PrmrrSize;
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if (prmrr_size > 0) {
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/*
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