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nb/intel/haswell: Guard DMIBAR/EPBAR macro parameters 

Add brackets around the parameters to avoid operation order problems.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I5e1a02ba2ebf468f0d80b7f1838766280b6b7b22
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45352
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-09-14 13:22:01 +02:00
parent a3cb322018
commit e5ec50c236
1 changed files with 6 additions and 6 deletions
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12
src/northbridge/intel/haswell/haswell.h
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@ -57,9 +57,9 @@
* EPBAR - Egress Port Root Complex Register Block * EPBAR - Egress Port Root Complex Register Block
*/ */
#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) #define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + (x)))
#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x)) #define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + (x)))
#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x)) #define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + (x)))
#define EPPVCCAP1 0x004 /* 32bit */ #define EPPVCCAP1 0x004 /* 32bit */
#define EPPVCCAP2 0x008 /* 32bit */ #define EPPVCCAP2 0x008 /* 32bit */
@ -88,9 +88,9 @@
* DMIBAR * DMIBAR
*/ */
#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) #define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + (x)))
#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x)) #define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + (x)))
#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x)) #define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + (x)))
#define DMIVCECH 0x000 /* 32bit */ #define DMIVCECH 0x000 /* 32bit */
#define DMIPVCCAP1 0x004 /* 32bit */ #define DMIPVCCAP1 0x004 /* 32bit */