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mb/google/nissa/var/pirrha: Add 4th DTT sensor 

Add 4th sensor device for DTT tuning.

BUG=b:292134655
TEST=Built and verified DTT tool could monitor the new sensor device

Change-Id: I62f50711af81dfc1566d655f6dcfc66f68dbc794
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
This commit is contained in:
Seunghwan Kim 2023-09-18 12:48:38 +09:00 committed by Felix Held
parent 37444566a7
commit e608a4f4fd
1 changed files with 3 additions and 0 deletions
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3
src/mainboard/google/brya/variants/pirrha/overridetree.cb
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@ -210,6 +210,7 @@ chip soc/intel/alderlake
register "options.tsr[0].desc" = ""Memory""
register "options.tsr[1].desc" = ""Charger""
register "options.tsr[2].desc" = ""Ambient""
register "options.tsr[3].desc" = ""Sub Charger""
# TODO: below values are initial reference values only
## Passive Policy
@ -218,6 +219,7 @@ chip soc/intel/alderlake
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000),
[2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000),
[3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000),
[3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 75, 5000),
}"
## Critical Policy
@ -226,6 +228,7 @@ chip soc/intel/alderlake
[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN),
}"
register "controls.power_limits" = "{