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mb/google/hatch/var/jinlon: Fix EPS detection and disablement 

Commit ebf14826
[mb/google/hatch/var/jinlon: Switch to using device pointers]
broke jinlon boards without an electronic privacy screen (EPS) by
disabling the parent device (iGPU) instead of the EPS when determined to
be not present via SKU ID.

Commit c5a3a4a6
[mb/google/hatch (baseboard): add ACPI backlight support]
broke EPS detection by adding a duplicate iGPU device to the devicetree,
resulting in the EPS entry being skipped.

Fix both of these issues by assigning the device alias to the EPS child
device, not the parent (iGPU). Rename the alias for clarity, and combine
the duplicate device definitions for the iGPU.

Test: build/boot google/jinlon SKU w/o EPS, observe GPU functional
in both firmware boot screens and Linux OS.

Change-Id: I0615ce361497abe6872085b0dec83292607e53dd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62593
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Matt DeVillier 2022-03-04 15:32:41 -06:00
parent 269b8e2cc5
commit e611905eb3
2 changed files with 5 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/google/hatch/variants/jinlon/mainboard.c
View File

@ -20,20 +20,20 @@ static bool eps_sku(uint32_t sku_id)
static void check_for_eps(uint32_t sku_id)
{
struct device *gfx_dev = DEV_PTR(igpu);
struct device *eps_dev = DEV_PTR(eps);
if (eps_sku(sku_id)) {
printk(BIOS_INFO, "SKU ID %u has EPS\n", sku_id);
return;
}
if (!gfx_dev) {
if (!eps_dev) {
printk(BIOS_ERR, "Error! No EPS dev, view-angle-management won't work\n");
return;
}
printk(BIOS_INFO, "SKU ID %u doesn't have EPS, disabling...\n", sku_id);
gfx_dev->enabled = 0;
eps_dev->enabled = 0;
}
void variant_devtree_update(void)

6
src/mainboard/google/hatch/variants/jinlon/overridetree.cb
View File

@ -69,10 +69,8 @@ chip soc/intel/cannonlake
register "ScsEmmcHs400Enabled" = "1"
device domain 0 on
device pci 02.0 alias igpu on # Integrated Graphics Device
register "gfx" = "GMA_DEFAULT_PANEL(0)"
end
device pci 02.0 on
register "gfx" = "GMA_DEFAULT_PANEL(0)"
chip drivers/gfx/generic
register "device_count" = "1"
register "device[0].name" = ""LCD""
@ -80,7 +78,7 @@ chip soc/intel/cannonlake
register "device[0].addr" = "0x80010400"
register "device[0].privacy.enabled" = "1"
register "device[0].privacy.gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E0)"
device generic 0 on end
device generic 0 alias eps on end
end
end # Integrated Graphics Device
device pci 14.0 on