mainboard/asus/kgpe-d16: Add initial Family 15h CPU support
Change-Id: I76f74ed4ae383f8b1f57eaaa2e025035002430f2 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11967 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Timothy Pearson
Stefan Reinauer
parent
3ff36b05cd
commit
e619a9ac9b
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@ -2,13 +2,14 @@ baud_rate = 115200
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debug_level = Spew
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multi_core = Enable
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slow_cpu = off
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compute_unit_siblings = Enable
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iommu = Disable
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nmi = Disable
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hypertransport_speed_limit = Auto
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max_mem_clock = DDR3-1600
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minimum_memory_voltage = 1.5V
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ECC_memory = Enable
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ECC_redirection = Disable
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ECC_redirection = Enable
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ecc_scrub_rate = 1.28us
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interleave_chip_selects = Enable
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interleave_nodes = Disable
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@ -26,8 +26,8 @@ entries
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401 1 e 1 interleave_chip_selects
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402 1 e 1 interleave_nodes
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403 1 e 1 interleave_memory_channels
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404 2 e 8 max_mem_clock
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406 1 e 2 multi_core
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404 4 e 8 max_mem_clock
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408 1 e 2 multi_core
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412 4 e 6 debug_level
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440 4 e 9 slow_cpu
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444 1 e 1 nmi
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@ -37,6 +37,7 @@ entries
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457 1 e 1 ECC_redirection
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458 4 e 11 hypertransport_speed_limit
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462 2 e 12 minimum_memory_voltage
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464 1 e 2 compute_unit_siblings
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477 1 e 1 ieee1394_controller
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728 256 h 0 user_data
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984 16 h 0 check_sum
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@ -74,10 +75,12 @@ enumerations
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6 6 Information
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6 7 Debug
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6 8 Spew
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8 0 DDR3-1600
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8 1 DDR3-1333
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8 2 DDR3-1066
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8 3 DDR3-800
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8 0 DDR3-1866
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8 1 DDR3-1600
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8 2 DDR3-1333
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8 3 DDR3-1066
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8 4 DDR3-800
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8 5 DDR3-667
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9 0 off
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9 1 87.5%
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9 2 75.0%
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@ -220,21 +220,25 @@ chip northbridge/amd/amdfam10/root_complex # Root complex
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device pci 18.2 on end
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device pci 18.3 on end
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device pci 18.4 on end
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device pci 18.5 on end
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device pci 19.0 on end # Socket 0 node 1
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device pci 19.1 on end
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device pci 19.2 on end
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device pci 19.3 on end
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device pci 19.4 on end
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device pci 19.5 on end
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device pci 1a.0 on end # Socket 1 node 0
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device pci 1a.1 on end
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device pci 1a.2 on end
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device pci 1a.3 on end
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device pci 1a.4 on end
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device pci 1a.5 on end
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device pci 1b.0 on end # Socket 1 node 1
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device pci 1b.1 on end
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device pci 1b.2 on end
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device pci 1b.3 on end
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device pci 1b.4 on end
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device pci 1b.5 on end
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end
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end
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end
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@ -19,7 +19,262 @@
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static void setup_mb_resource_map(void)
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{
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static const unsigned int register_values[] = {
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static const unsigned int fam15h_register_values[] = {
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/* Careful set limit registers before base registers which contain the enables */
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/* DRAM Limit i Registers
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* F1:0x44 i = 0
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* F1:0x4C i = 1
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* F1:0x54 i = 2
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* F1:0x5C i = 3
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* F1:0x64 i = 4
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* F1:0x6C i = 5
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* F1:0x74 i = 6
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* F1:0x7C i = 7
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* [ 2: 0] Destination Node ID
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* 000 = Node 0
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* 001 = Node 1
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* 010 = Node 2
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* 011 = Node 3
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* 100 = Node 4
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* 101 = Node 5
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* 110 = Node 6
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* 111 = Node 7
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* [ 7: 3] Reserved
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* [10: 8] Interleave select
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* specifies the values of A[14:12] to use with interleave enable.
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* [15:11] Reserved
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* [31:16] DRAM Limit Address i Bits 39-24
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* This field defines the upper address bits of a 40 bit address
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* that define the end of the DRAM region.
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*/
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// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007,
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/* DRAM Base i Registers
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* F1:0x40 i = 0
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* F1:0x48 i = 1
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* F1:0x50 i = 2
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* F1:0x58 i = 3
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* F1:0x60 i = 4
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* F1:0x68 i = 5
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* F1:0x70 i = 6
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* F1:0x78 i = 7
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* [ 0: 0] Read Enable
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* 0 = Reads Disabled
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* 1 = Reads Enabled
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* [ 1: 1] Write Enable
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* 0 = Writes Disabled
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* 1 = Writes Enabled
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* [ 7: 2] Reserved
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* [10: 8] Interleave Enable
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* 000 = No interleave
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* 001 = Interleave on A[12] (2 nodes)
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* 010 = reserved
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* 011 = Interleave on A[12] and A[14] (4 nodes)
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* 100 = reserved
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* 101 = reserved
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* 110 = reserved
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* 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
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* [15:11] Reserved
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* [31:16] DRAM Base Address i Bits 39-24
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* This field defines the upper address bits of a 40-bit address
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* that define the start of the DRAM region.
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*/
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// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000,
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/* Memory-Mapped I/O Limit i Registers
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* F1:0x84 i = 0
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* F1:0x8C i = 1
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* F1:0x94 i = 2
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* F1:0x9C i = 3
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* F1:0xA4 i = 4
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* F1:0xAC i = 5
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* F1:0xB4 i = 6
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* F1:0xBC i = 7
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* [ 2: 0] Destination Node ID
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* 000 = Node 0
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* 001 = Node 1
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* 010 = Node 2
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* 011 = Node 3
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* 100 = Node 4
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* 101 = Node 5
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* 110 = Node 6
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* 111 = Node 7
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* [ 3: 3] Reserved
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* [ 5: 4] Destination Link ID
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* 00 = Link 0
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* 01 = Link 1
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* 10 = Link 2
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* 11 = Link 3
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* [ 6: 6] Reserved
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* [ 7: 7] Non-Posted
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* 0 = CPU writes may be posted
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* 1 = CPU writes must be non-posted
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* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
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* This field defines the upp adddress bits of a 40-bit address that
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* defines the end of a memory-mapped I/O region n
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*/
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00000000,
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/* Memory-Mapped I/O Base i Registers
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* F1:0x80 i = 0
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* F1:0x88 i = 1
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* F1:0x90 i = 2
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* F1:0x98 i = 3
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* F1:0xA0 i = 4
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* F1:0xA8 i = 5
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* F1:0xB0 i = 6
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* F1:0xB8 i = 7
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* [ 0: 0] Read Enable
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* 0 = Reads disabled
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* 1 = Reads Enabled
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* [ 1: 1] Write Enable
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* 0 = Writes disabled
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* 1 = Writes Enabled
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* [ 2: 2] Cpu Disable
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* 0 = Cpu can use this I/O range
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* 1 = Cpu requests do not use this I/O range
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* [ 3: 3] Lock
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* 0 = base/limit registers i are read/write
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* 1 = base/limit registers i are read-only
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* [ 7: 4] Reserved
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* [31: 8] Memory-Mapped I/O Base Address i (39-16)
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* This field defines the upper address bits of a 40bit address
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* that defines the start of memory-mapped I/O region i
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*/
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00000000,
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/* PCI I/O Limit i Registers
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* F1:0xC4 i = 0
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* F1:0xCC i = 1
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* F1:0xD4 i = 2
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* F1:0xDC i = 3
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* [ 2: 0] Destination Node ID
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* 000 = Node 0
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* 001 = Node 1
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* 010 = Node 2
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* 011 = Node 3
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* 100 = Node 4
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* 101 = Node 5
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* 110 = Node 6
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* 111 = Node 7
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* [ 3: 3] Reserved
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* [ 5: 4] Destination Link ID
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* 00 = Link 0
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* 01 = Link 1
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* 10 = Link 2
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* 11 = Link 3
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* [11: 6] Reserved
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* [24:12] PCI I/O Limit Address i
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* This field defines the end of PCI I/O region n
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* [31:25] Reserved
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*/
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of cpu 0 --> AMD SR5690 */
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
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/* PCI I/O Base i Registers
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* F1:0xC0 i = 0
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* F1:0xC8 i = 1
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* F1:0xD0 i = 2
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* F1:0xD8 i = 3
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* [ 0: 0] Read Enable
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* 0 = Reads Disabled
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* 1 = Reads Enabled
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* [ 1: 1] Write Enable
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* 0 = Writes Disabled
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* 1 = Writes Enabled
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* [ 3: 2] Reserved
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* [ 4: 4] VGA Enable
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* 0 = VGA matches Disabled
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* 1 = matches all address < 64K and where A[9:0] is in the
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* range 3B0-3BB or 3C0-3DF independent of the base & limit registers
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* [ 5: 5] ISA Enable
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* 0 = ISA matches Disabled
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* 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
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* from matching agains this base/limit pair
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* [11: 6] Reserved
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* [24:12] PCI I/O Base i
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* This field defines the start of PCI I/O region n
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* [31:25] Reserved
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*/
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// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
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/* Config Base and Limit i Registers
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* F1:0xE0 i = 0
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* F1:0xE4 i = 1
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* F1:0xE8 i = 2
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* F1:0xEC i = 3
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* [ 0: 0] Read Enable
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* 0 = Reads Disabled
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* 1 = Reads Enabled
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* [ 1: 1] Write Enable
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* 0 = Writes Disabled
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* 1 = Writes Enabled
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* [ 2: 2] Device Number Compare Enable
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* 0 = The ranges are based on bus number
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* 1 = The ranges are ranges of devices on bus 0
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* [ 3: 3] Reserved
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* [ 6: 4] Destination Node
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* 000 = Node 0
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* 001 = Node 1
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* 010 = Node 2
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* 011 = Node 3
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* 100 = Node 4
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* 101 = Node 5
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* 110 = Node 6
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* 111 = Node 7
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* [ 7: 7] Reserved
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* [ 9: 8] Destination Link
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* 00 = Link 0
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* 01 = Link 1
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* 10 = Link 2
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* 11 - Link 3
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* [15:10] Reserved
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* [23:16] Bus Number Base i
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* This field defines the lowest bus number in configuration region i
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* [31:24] Bus Number Limit i
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* This field defines the highest bus number in configuration region i
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*/
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of cpu 0 --> AMD SR5690 */
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
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};
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static const unsigned int fam10h_register_values[] = {
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/* Careful set limit registers before base registers which contain the enables */
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/* DRAM Limit i Registers
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* F1:0x44 i = 0
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@ -275,6 +530,21 @@ static void setup_mb_resource_map(void)
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};
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int max;
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max = ARRAY_SIZE(register_values);
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setup_resource_map(register_values, max);
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uint8_t fam15h = 0;
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uint32_t family;
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family = cpuid_eax(0x80000001);
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family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
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if (family >= 0x6f)
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/* Family 15h or later */
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fam15h = 1;
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if (fam15h) {
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max = ARRAY_SIZE(fam15h_register_values);
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setup_resource_map(fam15h_register_values, max);
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} else {
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max = ARRAY_SIZE(fam10h_register_values);
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setup_resource_map(fam10h_register_values, max);
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}
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}
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@ -38,6 +38,7 @@
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#include <superio/nuvoton/common/nuvoton.h>
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#include <superio/nuvoton/nct5572d/nct5572d.h>
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#include <cpu/x86/bist.h>
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#include <smp/spinlock.h>
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// #include "northbridge/amd/amdk8/incoherent_ht.c"
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#include <southbridge/amd/sb700/sb700.h>
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#include <southbridge/amd/sb700/smbus.h>
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@ -206,20 +207,20 @@ void DIMMSetVoltages(struct MCTStatStruc *pMCTstat,
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if (pDCTstat->NodePresent && (node % 2)) {
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/* Set voltages */
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if (node_allowed_voltages & 0x8) {
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set_voltage = 1150;
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set_voltage = 0x8;
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set_ddr3_voltage(socket, 3);
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} else if (node_allowed_voltages & 0x4) {
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set_voltage = 1250;
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set_voltage = 0x4;
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set_ddr3_voltage(socket, 2);
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} else if (node_allowed_voltages & 0x2) {
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set_voltage = 1350;
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set_voltage = 0x2;
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set_ddr3_voltage(socket, 1);
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} else {
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set_voltage = 1500;
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set_voltage = 0x1;
|
||||
set_ddr3_voltage(socket, 0);
|
||||
}
|
||||
|
||||
/* Save final DIMM voltages for SMBIOS use */
|
||||
/* Save final DIMM voltages for MCT and SMBIOS use */
|
||||
if (pDCTstat->NodePresent) {
|
||||
for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) {
|
||||
pDCTstat->DimmConfiguredVoltage[dimm] = set_voltage;
|
||||
|
|
@ -233,6 +234,9 @@ void DIMMSetVoltages(struct MCTStatStruc *pMCTstat,
|
|||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Allow the DDR supply voltages to settle */
|
||||
udelay(100000);
|
||||
}
|
||||
|
||||
static void set_peripheral_control_lines(void) {
|
||||
|
|
@ -372,7 +376,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
|||
setup_mb_resource_map();
|
||||
post_code(0x36);
|
||||
|
||||
/* wait for all the APs core0 started by finalize_node_setup. */
|
||||
/* Wait for all the APs core0 started by finalize_node_setup. */
|
||||
/* FIXME: A bunch of cores are going to start output to serial at once.
|
||||
* It would be nice to fix up prink spinlocks for ROM XIP mode.
|
||||
* I think it could be done by putting the spinlock flag in the cache
|
||||
|
|
@ -384,6 +388,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
|||
sr5650_early_setup();
|
||||
sb7xx_51xx_early_setup();
|
||||
|
||||
if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) {
|
||||
/* Core0 on each node is configured. Now setup any additional cores. */
|
||||
printk(BIOS_DEBUG, "start_other_cores()\n");
|
||||
start_other_cores();
|
||||
post_code(0x37);
|
||||
wait_all_other_cores_started(bsp_apicid);
|
||||
}
|
||||
|
||||
if (IS_ENABLED(CONFIG_SET_FIDVID)) {
|
||||
msr = rdmsr(0xc0010071);
|
||||
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
|
||||
|
|
@ -393,11 +405,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
|||
|
||||
post_code(0x39);
|
||||
|
||||
#if IS_ENABLED(CONFIG_SET_FIDVID)
|
||||
if (!warm_reset_detect(0)) { // BSP is node 0
|
||||
init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
|
||||
} else {
|
||||
init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
|
||||
}
|
||||
#endif
|
||||
|
||||
post_code(0x3A);
|
||||
|
||||
|
|
@ -406,21 +420,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
|||
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) {
|
||||
/* Core0 on each node is configured. Now setup any additional cores. */
|
||||
printk(BIOS_DEBUG, "start_other_cores()\n");
|
||||
start_other_cores();
|
||||
post_code(0x37);
|
||||
wait_all_other_cores_started(bsp_apicid);
|
||||
}
|
||||
|
||||
post_code(0x38);
|
||||
|
||||
init_timer(); // Need to use TMICT to synconize FID/VID
|
||||
|
||||
sr5650_htinit();
|
||||
|
||||
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
|
||||
/* Reset for HT, FIDVID, PLL and errata changes to take effect. */
|
||||
if (!warm_reset_detect(0)) {
|
||||
printk(BIOS_INFO, "...WARM RESET...\n\n\n");
|
||||
soft_reset();
|
||||
|
|
|
|||
Loading…
Reference in New Issue