mediatek/mt8183: Add infra group DCM setting
Add infra group DCM (Dynamic Clock Management) settings, which slows down OR gate clocks while hardware is in idle state. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui. Change-Id: I4741dfb7b984deb92171f370e5fb2593829d74c2 Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: You-Cheng Syu <youcheng@google.com>
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@ -270,4 +270,13 @@ enum {
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SPI_HZ = MAINPLL_D5_D2_HZ,
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};
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enum {
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DCM_INFRA_BUS_MASK = 0x40907ffb,
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DCM_INFRA_BUS_ON = 0x40904203,
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DCM_INFRA_MEM_ON = 0x1 << 27,
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DCM_INFRA_P2PRX_MASK = 0xf,
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DCM_INFRA_PERI_MASK = 0xf03ffffb,
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DCM_INFRA_PERI_ON = 0xf03f83e3,
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};
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#endif /* SOC_MEDIATEK_MT8183_PLL_H */
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@ -344,6 +344,12 @@ void mt_pll_init(void)
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/* enable infrasys DCM */
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setbits_le32(&mt8183_infracfg->infra_bus_dcm_ctrl, 0x3 << 21);
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clrsetbits_le32(&mt8183_infracfg->infra_bus_dcm_ctrl,
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DCM_INFRA_BUS_MASK, DCM_INFRA_BUS_ON);
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setbits_le32(&mt8183_infracfg->mem_dcm_ctrl, DCM_INFRA_MEM_ON);
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clrbits_le32(&mt8183_infracfg->p2p_rx_clk_on, DCM_INFRA_P2PRX_MASK);
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clrsetbits_le32(&mt8183_infracfg->peri_bus_dcm_ctrl,
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DCM_INFRA_PERI_MASK, DCM_INFRA_PERI_ON);
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/* enable [11] for change i2c module source clock to TOPCKGEN */
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setbits_le32(&mt8183_infracfg->module_clk_sel, 0x1 << 11);
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