diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 0170eecffd..0987b41bf2 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -82,7 +82,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	FSPS_ARCH_UPD *pfsps_arch_upd = &supd->FspsArchUpd;
 	uint32_t enable_mask;
 
-	struct device *dev;
 	struct soc_intel_alderlake_config *config;
 	config = config_of_soc();
 	mainboard_update_soc_chip_config(config);
@@ -179,14 +178,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	pfsps_arch_upd->EnableMultiPhaseSiliconInit = 1;
 
 	/* Enable xDCI controller if enabled in devicetree and allowed */
-	dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
-	if (dev) {
-		if (!xdci_can_enable())
-			dev->enabled = 0;
-		params->XdciEnable = dev->enabled;
-	} else {
-		params->XdciEnable = 0;
-	}
+	if (!xdci_can_enable())
+		devfn_disable(pci_root_bus(), PCH_DEVFN_USBOTG);
+	params->XdciEnable = is_devfn_enabled(PCH_DEVFN_USBOTG);
 
 	/* PCH UART selection for FSP Debug */
 	params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;