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mb/google/var/gimble: Add gpios to lock 

Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.

BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
gimble boots successfully to kernel.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Idd398d819dcb30a3ec588ce2ef4562a728f99405
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Eric Lai 2022-02-07 15:44:37 +08:00 committed by Felix Held
parent 43e8807b6f
commit e6460a4777
1 changed files with 11 additions and 11 deletions
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22
src/mainboard/google/brya/variants/gimble/gpio.c
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@ -27,11 +27,11 @@ static const struct pad_config override_gpio_table[] = {
PAD_NC(GPP_A22, NONE), PAD_NC(GPP_A22, NONE),
/* B3 : PROC_GP2 ==> NC */ /* B3 : PROC_GP2 ==> NC */
PAD_NC(GPP_B3, NONE), PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG),
/* B5 : ISH_I2C0_SDA ==> NC */ /* B5 : ISH_I2C0_SDA ==> NC */
PAD_NC(GPP_B5, NONE), PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG),
/* B6 : ISH_I2C0_SCL ==> NC */ /* B6 : ISH_I2C0_SCL ==> NC */
PAD_NC(GPP_B6, NONE), PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG),
/* C3 : SML0CLK ==> NC */ /* C3 : SML0CLK ==> NC */
PAD_NC(GPP_C3, NONE), PAD_NC(GPP_C3, NONE),
@ -39,17 +39,17 @@ static const struct pad_config override_gpio_table[] = {
PAD_NC(GPP_C4, NONE), PAD_NC(GPP_C4, NONE),
/* D3 : ISH_GP3 ==> NC */ /* D3 : ISH_GP3 ==> NC */
PAD_NC(GPP_D3, NONE), PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
/* D5 : SRCCLKREQ0# ==> NC */ /* D5 : SRCCLKREQ0# ==> NC */
PAD_NC(GPP_D5, NONE), PAD_NC(GPP_D5, NONE),
/* D9 : ISH_SPI_CS# ==> NC */ /* D9 : ISH_SPI_CS# ==> NC */
PAD_NC(GPP_D9, NONE), PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
/* D15 : ISH_UART0_RTS# ==> NC */ /* D15 : ISH_UART0_RTS# ==> NC */
PAD_NC(GPP_D15, NONE), PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
/* D16 : ISH_UART0_CTS# ==> EN_WCAM_PWR */ /* D16 : ISH_UART0_CTS# ==> EN_WCAM_PWR */
PAD_CFG_GPO(GPP_D16, 1, DEEP), PAD_CFG_GPO_LOCK(GPP_D16, 1, LOCK_CONFIG),
/* D17 : UART1_RXD ==> NC */ /* D17 : UART1_RXD ==> NC */
PAD_NC(GPP_D17, NONE), PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG),
/* E0 : SATAXPCIE0 ==> NC */ /* E0 : SATAXPCIE0 ==> NC */
PAD_NC(GPP_E0, NONE), PAD_NC(GPP_E0, NONE),
@ -60,11 +60,11 @@ static const struct pad_config override_gpio_table[] = {
/* E7 : PROC_GP1 ==> NC */ /* E7 : PROC_GP1 ==> NC */
PAD_NC(GPP_E7, NONE), PAD_NC(GPP_E7, NONE),
/* E10 : THC0_SPI1_CS# ==> NC */ /* E10 : THC0_SPI1_CS# ==> NC */
PAD_NC(GPP_E10, NONE), PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG),
/* E16 : RSVD_TP ==> NC */ /* E16 : RSVD_TP ==> NC */
PAD_NC(GPP_E16, NONE), PAD_NC(GPP_E16, NONE),
/* E17 : THC0_SPI1_INT# ==> NC */ /* E17 : THC0_SPI1_INT# ==> NC */
PAD_NC(GPP_E17, NONE), PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG),
/* E18 : DDP1_CTRLCLK ==> NC */ /* E18 : DDP1_CTRLCLK ==> NC */
PAD_NC(GPP_E18, NONE), PAD_NC(GPP_E18, NONE),
/* E20 : DDP2_CTRLCLK ==> NC */ /* E20 : DDP2_CTRLCLK ==> NC */
@ -88,7 +88,7 @@ static const struct pad_config override_gpio_table[] = {
/* H9 : I2C4_SCL ==> NC */ /* H9 : I2C4_SCL ==> NC */
PAD_NC(GPP_H9, NONE), PAD_NC(GPP_H9, NONE),
/* H13 : I2C7_SCL ==> EN_PP3300_SD */ /* H13 : I2C7_SCL ==> EN_PP3300_SD */
PAD_CFG_GPO(GPP_H13, 1, DEEP), PAD_CFG_GPO_LOCK(GPP_H13, 1, LOCK_CONFIG),
/* H15 : DDPB_CTRLCLK ==> NC */ /* H15 : DDPB_CTRLCLK ==> NC */
PAD_NC(GPP_H15, NONE), PAD_NC(GPP_H15, NONE),
/* H17 : DDPB_CTRLDATA ==> NC*/ /* H17 : DDPB_CTRLDATA ==> NC*/