soc/intel/skylake: add PrmrrSize to chip config
Prmrr configuration is supported by Kabylake FSP-M with UPD provided. It is required as one of the SGX initialization steps in BIOS. BUG=chrome-os-partner:62438 BRANCH=NONE TEST=Tested on Eve, verified uncore PRMRR MSRs get programmed to set size and boot. Change-Id: I2b3dc7c92487505165ee429bd1a37bd60ceac8f3 Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Reviewed-on: https://review.coreboot.org/18361 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -376,6 +376,14 @@ struct soc_intel_skylake_config {
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/* Enable/Disable VMX feature */
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/* Enable/Disable VMX feature */
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u8 VmxEnable;
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u8 VmxEnable;
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/*
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* PRMRR size setting with three options
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* 0x02000000 - 32MiB
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* 0x04000000 - 64MiB
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* 0x08000000 - 128MiB
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*/
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u32 PrmrrSize;
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/* Statically clock gate 8254 PIT. */
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/* Statically clock gate 8254 PIT. */
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u8 clock_gate_8254;
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u8 clock_gate_8254;
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@ -139,6 +139,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg)
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m_cfg->RMT = config->Rmt;
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m_cfg->RMT = config->Rmt;
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m_cfg->DdrFreqLimit = config->DdrFreqLimit;
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m_cfg->DdrFreqLimit = config->DdrFreqLimit;
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m_cfg->VmxEnable = config->VmxEnable;
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m_cfg->VmxEnable = config->VmxEnable;
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m_cfg->PrmrrSize = config->PrmrrSize;
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for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
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for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
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if (config->PcieRpEnable[i])
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if (config->PcieRpEnable[i])
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mask |= (1<<i);
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mask |= (1<<i);
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