soc/intel/apollolake: Improve cold boot and S3 resume

FSP 2.0.7.1 provides UPD interface to execute IPC command. Configure
PmicPmcIpcCtrl for PMC to program PMIC PCH_PWROK delay from default
100ms to 10ms to improve cold boot and S3 resume performance.

BUG=b:118676361
CQ-DEPEND=CL:*703187
TEST=Verified system_resume_firmware_ec time reduction.

Change-Id: I05656c9083a855112120b7f1b0ec01c42f582409
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/29363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/soc/intel/apollolake/chip.c

@@ -567,6 +567,13 @@ static void glk_fsp_silicon_init_params_cb(
 	 * has set up. Hence skipping in FSP.
 	 */
 	silconfig->SkipSpiPCP = 1;
+
+	/*
+	 * FSP provides UPD interface to execute IPC command. In order to
+	 * improve boot performance, configure PmicPmcIpcCtrl for PMC to program
+	 * PMIC PCH_PWROK delay.
+	*/
+	silconfig->PmicPmcIpcCtrl = cfg->PmicPmcIpcCtrl;
 #endif
 }
 

src/soc/intel/apollolake/chip.h

@@ -156,6 +156,12 @@ struct soc_intel_apollolake_config {
 	 * (1) Power
 	 * (2) Power & Performance */
 	enum pnp_settings pnp_settings;
+
+	/* PMIC PCH_PWROK delay configuration - IPC Configuration
+	 * Upd for changing PCH_PWROK delay configuration : I2C_Slave_Address
+	 * (31:24) + Register_Offset (23:16) + OR Value (15:8) + AND Value (7:0)
+	 */
+	uint32_t PmicPmcIpcCtrl;
 };
 
 typedef struct soc_intel_apollolake_config config_t;

src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h

@@ -1715,9 +1715,15 @@ typedef struct {
 **/
   UINT8                       SkipSpiPCP;
 
-/** Offset 0x03AB
+/** Offset 0x03AB - PMIC PCH_PWROK delay configuration - IPC Configuration
+  Upd for changing PCH_PWROK delay configuration : I2C_Slave_Address (31:24) + Register_Offset
+  (23:16) + OR Value (15:8) + AND Value (7:0)
 **/
-  UINT8                       ReservedFspsUpd[5];
+  UINT32                      PmicPmcIpcCtrl;
+
+/** Offset 0x03AF
+**/
+  UINT8                       ReservedFspsUpd[1];
 } FSP_S_CONFIG;
 
 /** Fsp S SGX Configuration